A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.

A microelectronic device has a first die attached to a first die pad, and a second die attached to a second die pad. A magnetically permeable member is attached to a first coupler pad and a second coupler pad. A coupler component is attached to the magnetically permeable member. The first die pad, the second die pad, the first coupler pad, the second coupler pad, and the magnetically permeable member are electrically conductive. The first coupler pad is electrically isolated from the first die, from the second coupler pad, and from external leads of the microelectronic device. The second coupler pad is electrically isolated from the first die and from the external leads. The first die and the second die are electrically coupled to the coupler component. A package structure contains at least portions of the components of the microelectronic device and extends to the external leads.

A semiconductor device includes at least one transistor, a plurality of input wires, and a plurality of output wires. The at least one transistor has a plurality of input pads arranged along one side of the at least one transistor and a plurality of output pads arranged along another side of the at least one transistor facing the one side. The plurality of input wires are respectively connected to the plurality of input pads. The plurality of output wires are respectively connected to the plurality of output pads and have longer wire lengths than the plurality of input wires. Adjacent input wires of the plurality of input wires are arranged parallel to each other, and adjacent output wires of the plurality of output wires are arranged non-parallel to each other.

A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.

A semiconductor package includes a package substrate including a first substrate channel pad and a second substrate channel pad, a chip stack including a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips located on odd layers from among the plurality of semiconductor chips and second semiconductor chips located on even layers from among the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips includes a first chip channel pad, and each of the second semiconductor chips includes a second chip channel pad, first inter-chip connection wires configured to electrically connect the first chip channel pads of the first semiconductor chips to one another, second inter-chip connection wires configured to electrically connect the second chip channel pads of the second semiconductor chips to one another.

A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

A light-emitting diode (LED) package includes a first LED pixel including a plurality of first LED chips and a first pixel driving integrated circuit to drive the first LED chips according to an active matrix (AM) mode using entirety of a first frame period, wherein the first pixel driving integrated circuit includes a first storage area configured to store first frame data of each first LED chip, a second storage area configured to store duty ratio compensation data of each first LED chip, a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data and the duty ratio compensation data to generate PWM data, and a PWM data generator configured to adjust an emission duty ratio based on the PWM data.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.