The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

A power switch module includes a semiconductor die and a conductive busbar. The semiconductor die is electrically conductively mounted to the busbar. The module also includes a dielectric coolant fluid and the busbar and the semiconductor die mounted thereto are immersed in the dielectric coolant fluid.

Techniques are provided to form semiconductor devices having a multi-layer spacer structure. In an example, a semiconductor device includes a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor region. A spacer structure made up of one or more dielectric layers is present along a sidewall of the gate structure and along a sidewall of the source region or the drain region. The spacer structure has three different portions: a first portion along the sidewall of the gate, a second portion along the sidewall of the source or drain region, and a third portion that connects between the first two portions. The third portion of the spacer structure has a multi-layer configuration while the first and second portions have a fewer number of material layers.

An integrated circuit includes a plurality of standard cells including first and second standard cells arranged adjacent to each other in a first direction, and first, second, and third metal layers sequentially stacked in a vertical direction. At least one power segment is arranged adjacent a region where at least one of the first standard cell and the second standard cell is arranged. The at least one power segment is configured to provide power to the plurality of standard cells and is formed as a pattern of the third metal layer extending in a second direction.

Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.

An exemplary device includes a dielectric layer and a transmission line structure disposed in the dielectric layer. The transmission line structure includes a first metal line disposed between a second metal line and a third metal line. Dielectric islands are disposed in a first region and a second region of the dielectric layer. The first region of the dielectric layer is between the first metal line and the second metal line. The second region of the dielectric layer is between the first metal line and the third metal line. A dielectric constant of the dielectric islands is greater than a dielectric constant of the dielectric layer. The dielectric islands may be doped sections of the dielectric layer. In some embodiments, the dielectric islands in the first region are aligned with the dielectric islands in the second region along a direction perpendicular to a lengthwise direction of the first metal line.

The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.