A detection device comprises a substrate, a terminal part provided on the substrate and having a plurality of terminals, a first protection circuit unit provided on the substrate and having a plurality of first protection circuits, a selector unit provided on the substrate and having a plurality of selectors, a second protection circuit unit provided on the substrate and having a plurality of second protection circuits and a sensor unit provided on the substrate and having a plurality of sensors. The first protection circuit unit is provided between the terminal unit and the selector unit, and the second protection circuit unit is provided between selector unit and the sensor unit.

A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.

A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.

The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).

The present application provides a low-leakage static electricity releasing circuit, a display panel and a display device. T1, T2 and T3 that are connected in series are taken as a first group. T4, T5 and T6 that are connected in series are taken as a second group. The first group and the second group serve as releasing paths for static electricity with negative voltages and static electricity with positive voltages, respectively. When one of the groups releases the static electricity, the other group has small current leakage. This reduces the affection of a static electricity releasing circuit on the voltage of a signal line due to the current leakage, and is applicable to static electricity releasing for foldable areas of a flexible, foldable display screen.

The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).

The present application provides a low-leakage static electricity releasing circuit, a display panel and a display device. T1, T2 and T3 that are connected in series are taken as a first group. T4, T5 and T6 that are connected in series are taken as a second group. The first group and the second group serve as releasing paths for static electricity with negative voltages and static electricity with positive voltages, respectively. When one of the groups releases the static electricity, the other group has small current leakage. This reduces the affection of a static electricity releasing circuit on the voltage of a signal line due to the current leakage, and is applicable to static electricity releasing for foldable areas of a flexible, foldable display screen.

An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.