The present technique relates to an imaging element and a distance measurement module capable of reducing parasitic capacity._A distance measurement module includes: a first wiring that connects predetermined transistors in first adjacent pixels to a via formed in one of first adjacent pixels and connected to a wiring formed in another layer; and a second wiring that connects predetermined transistors in second adjacent pixels to a via formed in a pixel that is adjacent to one of second adjacent pixels and connected to a wiring formed in another layer, in which the first wiring is connected to a redundant wiring. The present technique can be applied to a distance measurement sensor that performs distance measurement, for example.

An image sensor pixel includes a substrate having a pixel electrode on a light receiving surface thereof, and a photoelectric conversion layer including a perovskite material, on the pixel electrode. A transparent electrode is provided on the photoelectric conversion layer, and a vertical electrode is provided, which is electrically connected to the pixel electrode and extends at least partially through the substrate. The photoelectric conversion layer includes a perovskite layer, a first blocking layer extending between the pixel electrode and the perovskite layer, and a second blocking layer extending between the transparent electrode and the perovskite layer. The perovskite material may have a material structure of ABX.sub.3, A.sub.2BX.sub.4, A.sub.3BX.sub.5, A.sub.4BX.sub.6, ABX.sub.4, or A.sub.n−1B.sub.nX.sub.3n+1, where: n is a positive integer in a range from 2 to 6; A includes at least one material selected from a group consisting of Na, K, Rb, Cs and Fr; B includes at least one material selected from a divalent transition metal, a rare earth metal, an alkaline earth metal, Ga, In, Al, Sb, Bi, and Po; and X includes at least one material selected from Cl, Br, and I.

A color filter is disposed on a substrate. An organic photodiode is disposed on the color filter. The organic photodiode includes an electrode insulating layer having a recess region on the substrate, a first electrode on the color filter, the first electrode filling the recess region of the electrode insulating layer, a second electrode on the first electrode, and an organic photoelectric conversion layer interposed between the first electrode and the second electrode. The first electrode includes a seam extending at a first angle from a side surface of the recess region of the electrode insulating layer.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

A photoelectric conversion apparatus includes pixels having adjacent first and second pixels. The pixels each include, in a semiconductor layer of a substrate, a photoelectric conversion portion that generates charges, a charge holding portion that holds the charges, and a floating diffusion layer that converts the charges into a voltage. At least parts of the charge holding portion in the first pixel and the floating diffusion layer in the second pixel, parts of the charge holding portion in the first pixel and the charge holding portion in the second pixel, and/or parts of the floating diffusion layer in the first pixel and the floating diffusion layer in the second pixel overlap each other without physically touching each other in a depth direction of the substrate in a state where a region for separating the at least parts of the charge holding portions and the floating diffusion layers is provided therebetween.

An image sensor includes a plurality of pixels, each pixel including a light sensing structure including first, second and third light sensing elements sequentially stacked on a substrate, the light sensing structure having a first surface adjacent to a readout circuit and a second surface including a light receiving portion between first and second circumferential portions, a first through via on the first circumferential portion, extending from the first surface to connect with the first light sensing element, and configured to transfer charges of the first light sensing element to the readout circuit, and a vertical transfer gate on a second circumferential portion and configured to transfer charges of the second light sensing element to the readout circuit, the first through via and the vertical transfer gate of each pixel being arranged in a 1-shaped or L-shaped pattern in the first and second circumferential portions.

An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

An imaging device includes: pixels that are disposed in a row direction and a column direction and that include a first pixel and a second pixel adjacent to the first pixel along the row direction; a shield electrode located between the first pixel and the second pixel; a first shield via that extends from the shield electrode. The first pixel includes: a first photoelectric conversion layer that converts incident light to generate charge; and a first pixel electrode that collects the charge generated thereby. The second pixel includes: a second photoelectric conversion layer that converts incident light to generate charge; and a second pixel electrode that collects the charge generated thereby. The shield electrode is electrically isolated from the first pixel electrode and the second pixel electrode, and the first shield via is located between the first pixel electrode and the second pixel electrode in a plan view.