Image sensor pixels having low full-well capacity and high sensitivity for applications such as DIS, qDIS, single/multi bit QIS. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate. Image sensor may also comprise an array of pixels, wherein each pixel comprises: a vertical bipolar structure including an emitter, base, collector configured for storing photocarriers in the base; and a reset transistor coupled to the base, configured to be completely reset of all free carriers using the reset transistor. The emitter may be configured as a pinning layer to facilitate full depletion of the base. Such image sensor pixels may have a full well capacity less than that giving good signal-to-noise ratio (SNR).

A pixel circuit including a photodiode, a first storage capacitor and a second storage capacitor is provided. The first storage capacitor discharges to a first output voltage in a first exposure time and to a third output voltage in a third exposure time. The second storage capacitor discharges to a second output voltage in a second exposure time and to a fourth output voltage in a fourth exposure time. The first and second exposure times are included in a first frame period. The third and fourth exposure times are included in a second frame period. The second frame period is a next frame period of the first frame period. In the first frame period, the first exposure time is subsequent to the second exposure time. In the second frame period, the third exposure time is prior to the fourth exposure time.

Described is an arrangement for registering light, comprising: a MOS-transistor structure having a first source/drain region, a second source/drain region, and a bulk region at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region charge carriers are generated in dependence of light impinging on the bulk region, wherein the generated charge carriers control a current flowing from the first source/drain region to the second source/drain region via at least a portion of the bulk region.

An imaging device includes at least one pixel having a phototransistor which converts light energy into signal charge and varies an amplification factor relative to the intensity of the received light energy, wherein the signal charge of the phototransistor is read out while receiving the light energy with the phototransistor for each pixel.

Disclosed are a semiconductor device and an image sensor including the same. The semiconductor device includes a device isolation layer defining an active region on a semiconductor substrate, a gate electrode crossing the active region, a gate insulating pattern between the gate electrode and the semiconductor substrate, a first impurity region provided at a first side of the gate electrode in the active region, and a second impurity region provided at a second side of the gate electrode in the active region, and the gate insulating pattern includes a first edge portion adjacent to a first sidewall of the device isolation layer, a second edge portion adjacent to a second sidewall of the device isolation layer, and a center portion between the first and second edge portions, and the first edge portion has a first thickness, and the second edge portion has a second thickness smaller than the first thickness.

Provided is a display device or a display system capable of displaying images along a curved surface, a display device or a display system capable of displaying images seamlessly in the form of a ring, or a display device or a display system that is suitable for increasing in size. The display device includes a display panel. The display panel includes a first part and a second part and is flexible. The first part can display images. The second part can transmit visible light. The display panel is curved so that the second part and the first part overlap with each other.

A computational pixel imaging device that includes an array of pixel integrated circuits for event-based detection and imaging. Each pixel may include a digital counter that accumulates a digital number, which indicates whether a change is detected by the pixel. The counter may count in one direction for a portion of an exposure and count in an opposite direction for another portion of the exposure. The imaging device may be configured to collect and transmit key frames at a lower rate, and collect and transmit delta or event frames at a higher rate. The key frames may include a full image of a scene, captured by the pixel array. The delta frames may include sparse data, captured by pixels that have detected meaningful changes in received light intensity. High speed, low transmission bandwidth motion image video can be reconstructed using the key frames and the delta frames.

A photo detector having a substrate and a first structure formed on the substrate. The first structure includes an emitter layer formed on the substrate and a base layer formed on the emitter layer. Further, the first structure includes a collector layer formed on the base layer. The collector layer has a plasmonic structure. The plasmonic structure includes a first plurality of mesa structures. Each of the mesa structures of the first plurality of mesa structures includes a second plurality of mesa structures having ridges arranged in a regularly repeating pattern.

An image sensor uses a pixel circuit which includes a BJT phototransistor having multiple selectable beta values. The BJT is one semiconductor device includes: a substrate having a first conductivity type; a first well having the first conductivity type; a collector electrode having the first conductivity type in the first well; a second well having a first concentration of a second conductivity type; a first emitter electrode having the first conductivity type in the second well; a base electrode having the second conductivity type in the second well; a third well having a second concentration of the second conductivity type, wherein the second concentration is different from the first concentration; and a second emitter electrode having the first conductivity type in the third well.

A stereo imaging system includes an optical assembly and a computational pixel imager (CPI) having a plurality of pixels. Each pixel includes a light sensor and counters that convert a photocurrent from the light sensor to a digital signal. The optical assembly, which directs light from a light field to the CPI, includes an optical field combiner and first and second primary lens assemblies, which are configured to receive first and second portions of the light from the light field, respectively, and to direct the first and second portions of the light to the optical field combiner. The optical field combiner includes a modulator configured to modulate the first and second portions of the light and to direct modulated first and second portions of the light onto the CPI. The counters are configured to perform digital signal processing on the digital signal.