A solid-state imaging element (100) includes a first photoelectric conversion unit and a second photoelectric conversion unit (600). The first and second photoelectric conversion units (500, 600) are joined at joint surfaces facing each other, and include an upper electrode (502, 602), a lower electrode (508A, 608), a photoelectric conversion film (504, 604), and a storage electrode (510, 610). The lower electrode (508A) of the first photoelectric conversion unit (500) is connected to a charge storage unit (314) via a first through electrode (460A, 460B) penetrating a semiconductor substrate (300). The lower electrode (608) of the second photoelectric conversion unit (600) is connected to the charge storage unit (314) via: a second electrode (673) provided on a joint surface of the second photoelectric conversion unit (600); a first electrode (573) provided on a joint surface of the first photoelectric conversion unit (500); a second through electrode (560) penetrating the first photoelectric conversion unit (500); and the first through electrode (460A, 460B).

To improve image quality of image data in a solid-state image sensor that detects an address event. The solid-state image sensor includes a photodiode, a pixel signal generation unit, and a detection unit. In the solid-state image sensor, the photodiode generates electrons and holes by photoelectric conversion. The pixel signal generation unit generates a pixel signal having a voltage according to an amount of one of the electrons and the holes. The detection unit detects whether or not a change amount in the other of the electrons and the holes has exceeded a predetermined threshold and outputs a detection signal.

Provided is a photoelectric conversion device including: a photoelectric conversion portion in a substrate that photoelectrically converts incident light to generate charges; a transfer transistor including a control electrode on the substrate that transfers the charges from the photoelectric conversion portion; wiring layers above the control electrode; a first wiring in a first wiring layer of the wiring layers that is the closest to the substrate; and a drive wiring in a second wiring layer above the first wiring layer, a control signal for controlling the transfer transistor being transferred to the control electrode via the drive wiring and first wiring and, in a plan view, at least part of the first wiring overlapping with at least part of the control electrode and at least part of an edge of the first wiring extending along an edge of the control electrode on a side facing the photoelectric conversion portion.

There is provided a solid-state imaging device that includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.

A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×10.sup.15 cm.sup.−3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

A device for determining the surface topology and associated color of a structure, such as a teeth segment, includes a scanner for providing depth data for points along a two-dimensional array substantially orthogonal to the depth direction, and an image acquisition means for providing color data for each of the points of the array, while the spatial disposition of the device with respect to the structure is maintained substantially unchanged. A processor combines the color data and depth data for each point in the array, thereby providing a three-dimensional color virtual model of the surface of the structure. A corresponding method for determining the surface topology and associate color of a structure is also provided.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.