Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

A transistor device and a method for producing thereof are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer; a plurality of trenches each extending from a first surface of the first semiconductor layer into the first semiconductor layer; and a plurality of transistor cells each coupled to a source node. The first semiconductor layer includes a plurality of mesa regions each formed between two neighboring ones of the trenches, in each of the mesa regions, at least one of the plurality of transistor cells is at least partially integrated, each of the transistor cells is connected to the source node via a respective source contact, and each of the source contacts is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

A multi-trench super junction IGBT device includes a metallization collector, a P-type substrate, a first N-type epitaxial layer located above the P-type substrate and a second N-type epitaxial layer located above the first N-type epitaxial layer. The second N-type epitaxial layer includes at least a first dummy MOS cell unit and a MOS cell unit, wherein the first dummy MOS cell unit includes a trench formed by reactive ion etching, a thermally grown gate oxide layer provided inside the trench and deposited heavily doped polysilicon located in the gate oxide layer.

In an entire intermediate region between an active region and an edge termination region, a p.sup.+-type region is provided between a p-type base region and a parallel pn layer. The p.sup.+-type region is formed concurrently with and in contact with p.sup.+-type regions for mitigating electric field near bottoms of gate trenches. The p.sup.+-type region has portions that face, respectively, n-type regions and p-type regions of a parallel pn layer in a depth direction Z and at the portions, has protrusions that protrude toward the parallel pn layer. N-type current spreading regions extend in the entire intermediate region from the active region and are between the p.sup.+-type region and the parallel pn layer, positioned between protrusions of the p.sup.+-type region. The impurity concentration of the n-type current spreading regions in the gate region is higher than that of those in other regions. Thus, avalanche capability may be enhanced.

A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.

The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

A semiconductor device includes a MOSFET including a drift layer, a channel layer, a trench gate structure, a source layer, a drain layer, a source electrode, and a drain electrode. The trench gate structure includes a trench penetrating the channel layer and protruding into the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film. A portion of the trench protruding into the drift layer is entirely covered with a well layer, and the well layer is connected to the channel layer.

A field effect transistor includes a semiconductor substrate and multiple trenches disposed at a top surface of the semiconductor substrate. The trenches extend in a first direction at the top surface of the semiconductor substrate, and are disposed to be spaced apart in a direction perpendicular to the first direction. Connection regions are disposed below body regions. The connection regions extend in a second direction intersecting the first direction in a top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the second direction. Field relaxation regions are disposed below the connection regions and the trenches. The field relaxation regions extend in a third direction intersecting the first direction and the second direction in the top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the third direction.

A semiconductor device includes: a substrate (10); a semiconductor layer (20) disposed on a main surface of this substrate (10); and a first main electrode (30) and a second main electrode (40), which are disposed on the substrate (10) separately from each other with the semiconductor layer (20) sandwiched therebetween and are individually end portions of a current path of a main current flowing in an on-state. The semiconductor layer (20) includes: a first conductivity-type drift region (21) through which a main current flows; a second conductivity-type column region (22) that is disposed inside the drift region (21) and extends in parallel to a current path; and an electric field relaxation region (23) that is disposed in at least a part between the drift region (21) and the column region (22) and is either a low-concentration region in which an impurity concentration is lower than in the same conductivity-type adjacent region or a non-doped region.