A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

A semiconductor includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern, the source/drain pattern being in contact with the sheet patterns, and gate structures on opposite sides of the source/drain pattern, the gate structures being spaced apart from each other along a second direction and including gate electrodes that surround the sheet patterns, wherein the source/drain pattern includes a first epitaxial region having at least one of antimony and bismuth, the first epitaxial region having a bottom part in contact with the lower pattern, but not with the sheet patterns, and a thickness of the bottom part increasing and decreasing away from the gate structures in the second direction, and a second epitaxial region on the first epitaxial region, the second epitaxial region including phosphorus.

FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.