A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.

A support substrate includes an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer. A back side of an integrated circuit chip is mounted to an upper surface of the support substrate at a die attach location. The upper surface of the support substrate includes a cavity located within the die attach location, where the cavity extends under the back side of the integrated circuit chip. The cavity is defined by an area where the solder mask layer and at least a portion of the electrically conductive layer have been removed. Bonding wires connect connection pads on a front side of the integrated circuit chip to connection pad on the upper surface of the support substrate.

A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.

A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a redistribution layer on the package substrate, a vertical connection terminals that connects the package substrate to the redistribution layer, a first semiconductor chip between the package substrate and the redistribution layer, a first molding layer that fills a space between the package substrate and the redistribution layer, a second semiconductor chip on the redistribution layer, a third semiconductor chip on the second semiconductor chip, a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip, and a second molding layer on the redistribution layer and covering the second semiconductor chip and the third semiconductor chip.

A semiconductor device includes an insulating substrate, a wiring, a semiconductor chip and a resin layer. The wiring is provided on the insulating substrate. The wiring board includes (i) an insulating material and (ii) a pad exposed relative to the insulating material and electrically connected to the wiring. A height of the insulating material in a vertical direction of the wiring board varies along the wiring board. The semiconductor chip includes a bump connected to the pad on a first surface of the semiconductor chip. The resin layer covers a periphery of the bump between the wiring board and the semiconductor chip.

A radio frequency (RF) chip package includes: an RF die; a first peripheral circuit chip; a second peripheral circuit chip; a substrate having a -shaped step formed on a portion thereof so that the RF die is mounted on top of the step of the substrate and the first peripheral circuit chip and the second peripheral circuit chip are mounted on top of the substrate where no step is formed; a first mutual inductance controller for controlling the dimension of the mutual inductance between the first peripheral circuit chip and the RF die; and a second mutual inductance controller for controlling the dimension of the mutual inductance between the second peripheral circuit chip and the RF die.

The present disclosure relates to a substrate with an integrated heat spreader. The disclosed substrate includes a substrate core, at least one connecting structure, and a heat spreader. The substrate core has a top surface and a bottom surface opposite the top surface of the substrate. The at least one connecting structure extends through the substrate core from the top surface of the substrate core to the bottom surface of the substrate core. And the heat spreader extends through the substrate core from the top surface of the substrate core to a bottom level that is below the bottom surface of the substrate core.

A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.