Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

The application describes MEMS transducer having a flexible membrane and which seeks to alleviate and/or redistribute stresses within the membrane layer. A membrane having a first/active region and a second/inactive region is described.

Provided is a package device, relating to the technical field of lamp beads. The package device comprises an SMD holder, wherein the SMD holder is a hollow housing with one end opened; and the material of sidewalls of the SMD holder is transparent plastic. In the package device provided by the present invention, a transparent material is provided as the material of the sidewalls of the SMD holder, and light generated after a chip is powered on can be partially transmitted out through the sidewalls of the SMD holder, avoiding blocking of the light generated after the chip is powered on by the sidewalls of the SMD holder, thereby increasing transmittance of light from the chip.

In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.

Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.

A display apparatus includes a substrate having a display area and a peripheral area surrounding the display area, a first initialization voltage line on the substrate, an organic film layer on the first initialization voltage line and having a first contact hole exposing at least a portion of the first initialization voltage line, and a bridge wiring on the organic film layer corresponding to the peripheral area, and in contact with the first initialization voltage line through the first contact hole, wherein the organic film layer corresponding to the peripheral area has a groove or dummy hole, each of the groove and the dummy hole being adjacent to the first contact hole.