A semiconductor device includes: a multilayer wiring substrate including a plurality of wiring layers; a first semiconductor chip disposed on the wiring substrate; and a bonding layer bonding the first semiconductor chip to the wiring substrate. A trace formed on the wiring substrate includes a first trace width portion and a second trace width portion, a width of the first trace width portion being greater than the second trace width portion.

A semiconductor package may be presented. The semiconductor package includes a first dielectric layer including a first surface and a second surface. First and second conductive lands are disposed on the first surface of the first dielectric layer. A first column formed by the first conductive lands and a second column formed by the second conductive lands are spaced apart from each other. Outer traces extend from the second conductive lands, and inner traces are disposed on the second surface of the first dielectric layer. Vias penetrate the first dielectric layer and respectively connect the first conductive lands to the inner traces. A semiconductor die is disposed on the first surface of the first dielectric layer.

The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.

A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.

In an embodiment A package includes a casing having an opening and enclosing a cavity, a die accommodated in the cavity and a membrane attached to the casing, the membrane being air-permeable, covering and sealing the opening, wherein the membrane is configured to allow only a lateral gas flow, and wherein a blocking member is configured to block a vertical gas flow through the membrane into the cavity, the blocking member tightly covering a surface of the membrane at least in an area comprising the opening.

A radio-frequency module includes a multilayer substrate, a first semiconductor device, a second semiconductor device, a first mold layer, and a second mold layer. The multilayer substrate includes a plurality of stacked layers, and has a first major face and a second major face. The first mold layer seals the first semiconductor device. The second mold layer seals the second semiconductor device. The first major face includes a first recess. The first semiconductor device is mounted over a bottom face of the first recess. The second semiconductor device is mounted over the first major face so as to overlie the first recess. The first semiconductor device is connected with a metallic via that extends through a portion of the multilayer substrate from the bottom face of the first recess to the second major face. The first mold layer and the second mold layer are made of different materials.

In a semiconductor package, flow guiding strips are provided on a guiding area of a flexible substrate to separate a chip and the flexible substrate such that a filling material flowing between the chip and the flexible substrate can squeeze out the air between the chip and the flexible substrate to improve the reliability of the semiconductor package.

A radio-frequency module includes a multilayer substrate, a first semiconductor device, a second semiconductor device, and a metal layer. The multilayer substrate includes a plurality of stacked layers, and has a first major face and a second major face. The first major face includes a first recess. The first semiconductor device is mounted over a bottom face of the first recess. The second semiconductor device is mounted over the first major face so as to overlie the first recess. The first semiconductor device is connected with a metallic via that extends through a portion of the multilayer substrate from the bottom face of the first recess to the second major face. The metal layer is disposed between the first semiconductor device and the second semiconductor device so as to overlie the first recess.

A radio-frequency module includes a multilayer substrate, a first semiconductor device, and a second semiconductor device. The multilayer substrate includes a plurality of stacked layers, and has a first major face and a second major face. The first semiconductor device includes a first power amplifier circuit. The second semiconductor device includes at least one of a low-noise amplifier circuit, a switching circuit, or a control circuit. The first major face includes a first recess. The first semiconductor device is mounted over a bottom face of the first recess. The second semiconductor device is mounted over the first major face so as to overlie the first recess. The first semiconductor device is connected with a metallic via that extends through a portion of the multilayer substrate from the bottom face of the first recess to the second major face.

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.