The invention discloses a semiconductor package structure including a package carrier, at least one electronic component, a packaging layer, a support component and a shielding layer. The electronic component is disposed on a first surface of the package carrier. The packaging layer is disposed on the first surface and covers the electronic component. The support component is embedded in the packaging layer to surround the electronic component. An end surface of the support component is electrically connected to a build-up circuit and electrically grounded. A patterned metal layer of the shielding layer is electrically connected to the support component. The shielding range of the patterned metal layer covers at least electronic component. A shielding space, which covers the electronic component, is formed by the support component and the shielding layer. In addition, a semiconductor EMI shielding component and a method of making a semiconductor package structure are also disclosed.

A base member for a light emitting device includes a bottom part and a frame part. The frame part has an upper surface, a lower surface, and a step portion. The frame part has a bonding surface bonded to the bottom part, and defining a planar surface of the step portion at a lower surface side, first and second inner surfaces, a first planar surface defining a planar surface of the step portion at an upper surface side, and first and second electrode layers electrically connected to each other, the second electrode layer being disposed on the first planar surface while the first electrode layer being not disposed on the first planar surface. The step portion extends along an entire periphery of the frame part in a bottom view, and the step portion does not extend along the entire periphery of the frame part in a top view.

A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.

A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

A monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding is provided. In an exemplary aspect, an ETL MMIC according to this disclosure includes a MMIC substrate having an active side, an ETL dielectric layer covering the active side, and a topside ground plane over the ETL dielectric layer. The active side includes one or more transmission lines or other components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in an external circuit assembly. The topside ground plane in the ETL MMIC provides shielding to reduce such electromagnetic coupling. The topside ground plane can also facilitate improved thermal paths for heat dissipation, such as through a redistribution layer (RDL) to a next higher assembly (NHA) and/or through a backside ground plane of the MMIC substrate.

A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.

A substrate for an LED emitter includes a body with a recess region formed therein. Bonding pads are disposed within the recess region, including LED bonding pads for LEDs and supporting chip bonding pads for one or more semiconductor chips that provide supporting circuitry (e.g., driver and/or controller circuitry) to support operation of the LEDs. External electrical contacts can be disposed outside the recess region. Electrical paths, disposed at least partially within the body of the substrate, connect the external electrical contacts to a first subset of the supporting chip bonding pads and connect a second subset of the supporting chip bonding pads to the plurality of LED bonding pads such that one or more supporting chips connected to the controller pads can be operated to deliver different operating currents to different ones of the LEDs.

Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.