A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.

The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.

The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.

A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.

Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.

Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.

A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.

Embodiments of the present application provide the chip packaging structure, the chip module and the electronic terminal. In the chip packaging structure, the chip is accommodated in the trench of the substrate to decrease the thickness and volume of the chip packaging structure; and the plastic package is provided on the surface of the substrate on which the chip is disposed to plastically package the chip, which not only ensures the structural strength of the chip packaging structure, but also reduces the warpage that may be caused due to the decrease of the thickness of the chip packaging structure as much as possible. In addition, the surface of the plastic package is treated to be a flat surface, such that the chip module has good flatness and the adaptability of the chip module is improved.