There are provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where a connection section used for the connection to a semiconductor element is arranged and a manufacturing method for a semiconductor module. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have through holes where sealing resins are formed, the sealing resins connecting adjacent housing sections and the sealing resin formed in the through hole being continuous with the sealing resins formed in the housing sections.

A semiconductor device includes a semiconductor element, at least one first resin member, and at least one conducting wire. The semiconductor element includes a front electrode and a body part. The at least one first resin member is disposed on a second surface of the front electrode. The at least one conducting wire includes a joining part. The at least one first resin member includes a convex part. The convex part protrudes from the front electrode in a direction away from the body part. The at least one conducting wire includes a concave part. The concave part is adjacent to the joining part. The concave part extends along the convex part. The concave part is fitted to the convex part.

A method of forming a package on a package structure includes applying a no-reflow underfill (NUF) layer over a substrate, wherein the substrate has at least one first bump and a plurality of second bumps surrounding the at least one first bump. The method further includes bonding a semiconductor die to the at least one first bump. The method further includes bonding an interposer frame to the plurality of second bumps, wherein the interposer frame surrounds the semiconductor die, wherein the semiconductor die is disposed in an opening of the interposer frame.

A transistor (2) and a matching circuit substrate (3-6) are provided on a base plate (1) and connected to each other. A frame (15) is provided on the base plate (1) and surrounds the transistor (2) and the matching circuit substrate (3-6). The frame (15) has a smaller linear expansion coefficient than that of the base plate (1). A screwing portion (17) is provided in the frame (15). A size of the base plate (1) is smaller than that of the frame (15).

A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.

A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a first circuit board having an opening extending through the first circuit board. A Chemical Vapor Deposition Diamond (CVDD) window extends within the opening. A layer of thermally conductive paste extends over the CVDD window. A semiconductor die extends over the layer of thermally conductive paste such that a hot-spot on the semiconductor die overlies the CVDD window.

A semiconductor package includes a redistribution wiring layer having redistribution wirings, a semiconductor chip on the redistribution wiring layer, a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings, and an antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another.

A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Semiconductor systems having anti-warpage frames (and associated systems, devices, and methods) are described herein. In one embodiment, a semiconductor system includes (a) a printed circuit board (PCB) having a first side and a second side opposite the first side, and (b) at least one memory device attached to the PCB at the first side of the PCB. The semiconductor system further includes a frame structure attached to the PCB at the first side of the PCB and proximate the at least one memory device. The frame structure can be configured to resist warpage of the PCB, for example, when the semiconductor system is heated to attach the at least one memory device to the PCB.

A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.