A semiconductor device includes a first semiconductor chip including a plurality of first control electrodes, each of which is disposed at a respective one of corner portions on a first front surface thereof, a first output electrode disposed on the first front surface, and a first input electrode disposed on a first rear surface thereof, a second semiconductor chip including a plurality of second control electrodes, each of which is disposed at a respective one of corner portions on a second front surface thereof, a second output electrode disposed on the second front surface, and a second input electrode disposed on a second rear surface thereof, the second semiconductor chip being disposed adjacent to the first semiconductor chip, and a first connection wire which connects one of the first control electrodes and one of the second control electrodes.

A packaged integrated circuit is provided. The packaged integrated circuit includes a die, a package including a base, a lid, and a plurality of package leads, and die attach adhesive for securing the die to the package base. the die includes a plurality of die pads. The die is secured to the base with the die attach adhesive. After the die is secured to the base, at least one of the plurality of die pads is electrically connected to at least one of the plurality of package leads with a printed bond connection. After printing the bond connection, the lid is sealed to the base.

Provided is a method for bonding an insulated coating wire, which is capable of stably bonding a metal wire in an insulated coating wire and an electrode. One aspect of the present invention provides a method for bonding an insulated coating wire for electrically connecting a first electrode 12 and a second electrode to each other by an insulated coating wire 11 in which a metal wire is coated with an organic substance, the method including: a step (a) for placing the insulated coating wire 11 onto the first electrode 12; a step (b) for exposing a metal wire from the insulated coating wire; and a step (c) for forming a first bump over the exposed metal wire and the first electrode to electrically connect the metal wire to the first electrode.

The embodiments described herein provide a device and method for an integrated white colored electromagnetic radiation source using a combination of laser diode excitation sources based on gallium and nitrogen containing materials and light emitting source based on phosphor materials. A violet, blue, or other wavelength laser diode source based on gallium and nitrogen materials may be closely integrated with phosphor materials, such as yellow phosphors, to form a compact, high-brightness, and highly-efficient, white light source. The phosphor material is provided with a plurality of scattering centers scribed on an excitation surface or inside bulk of a plate to scatter electromagnetic radiation of a laser beam from the excitation source incident on the excitation surface to enhance generation and quality of an emitted light from the phosphor material for outputting a white light emission either in reflection mode or transmission mode.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

The embodiments described herein provide a device and method for an integrated white colored electromagnetic radiation source using a combination of laser diode excitation sources based on gallium and nitrogen containing materials and light emitting source based on phosphor materials. A violet, blue, or other wavelength laser diode source based on gallium and nitrogen materials may be closely integrated with phosphor materials, such as yellow phosphors, to form a compact, high-brightness, and highly-efficient, white light source. The phosphor material is provided with a plurality of scattering centers scribed on an excitation surface or inside bulk of a plate to scatter electromagnetic radiation of a laser beam from the excitation source incident on the excitation surface to enhance generation and quality of an emitted light from the phosphor material for outputting a white light emission either in reflection mode or transmission mode.

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.