A plurality of lead pins (2a-d) penetrates through a stem (1) having a circular shape and includes a signal lead pin (2a,2b). A block (4) is provided on an upper surface of the stem. A waveguide light receiving device (9) is provided on a side surface of the block. An amplifier (6) is provided on the side surface of the block and amplifies an electric signal output from the waveguide light receiving device. A first relay substrate is provided on the upper surface of the stem and arranged between the block and the signal lead pin. A first transmission line (12a,12b) is provided on the first relay substrate. A first wire (10f,10g) connects one end of the first transmission line and an output terminal of the amplifier. A second wire (10h,10i) connects the other end of the first transmission line (12a,12b) and the signal lead pin.

In a ranging image sensor, each pixel includes an avalanche multiplication region, a charge distribution region, a pair of first charge transfer regions, a pair of second charge transfer regions, a well region, a photogate electrode, a pair of first transfer gate electrodes, and a pair of second transfer gate electrodes. The first multiplication region of the avalanche multiplication region is formed so as to overlap the charge distribution region and so as not to overlap the well region in the Z direction. The second multiplication region of the avalanche multiplication region is formed so as to overlap the charge distribution region and the well region in the Z direction.

A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.

A sensor chip includes a sensor pixel. The sensor pixel includes an avalanche photodetector. A circuit is adjacent to the avalanche photodetector. The circuit is coupled to the avalanche photodetector. An isolation structure at least partially encloses the circuit and is between the avalanche photodetector and the circuit.

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

A focal-plane array includes an array of pixels. Each pixel includes an avalanche-type diode on a first layer, a read-out circuit (ROIC) on a second layer, and a power-supply circuit on a middle layer stacked between the first layer and the second layer. Since each pixel includes the avalanche-type diode, the ROIC, and the power-supply circuit on different layers circuitry for each pixel is in a top-down footprint of the pixel. Thus a consistent bias voltage to each pixel, decouples the avalanche-type diodes of the different pixels to eliminate crosstalk between adjacent pixels, and allows for individual control of each pixel.

A focal-plane array includes an array of pixels. Each pixel includes an avalanche-type diode on a first layer, a read-out circuit (ROIC) on a second layer, and a power-supply circuit on a middle layer stacked between the first layer and the second layer. Since each pixel includes the avalanche-type diode, the ROIC, and the power-supply circuit on different layers circuitry for each pixel is in a top-down footprint of the pixel. Thus a consistent bias voltage to each pixel, decouples the avalanche-type diodes of the different pixels to eliminate crosstalk between adjacent pixels, and allows for individual control of each pixel.