A p-n junction based III-nitride device in which the p-type layers adjacent to the n-type layers are activated by thermal annealing with a porous n-type tunnel junction layer or layers. The porosity of the n-type tunnel junction layer(s) allows for gas exchange to occur, allowing efficient p-type nitride semiconductor activation. This porosification and activation step can be inserted wherever desired into an existing fabrication process for an LED, laser diode, or any other nitride semiconductor device. In one example, the device comprises multiple LED structures grown successively, separated by tunnel junctions and the buried p-type layers are activated by thermal annealing with adjacent porous n-type layers. Using this method, efficient monolithic multi-color LEDs can be formed.

The invention is a small-sized vertical light emitting diode chip with high energy efficiency, wherein a PN junction structure is arranged on a light-emitting region platform of an interface structure; a highly reflective metal layer is arranged under the light-emitting region platform; the interface structure is provided with a P-type ohmic contact area under an outwardly extending platform adjacent to the light-emitting region platform; an insulating layer is formed on the outwardly extending platform; an N-type ohmic contact electrode is in ohmic contact with the PN junction structure and covers the border covering region at a position opposite to the outwardly extending platform; the current conduction is achieved diagonally on the opposite sides by locally diagonally symmetric geometric positioning of the N-type ohmic contact electrode and the P-type ohmic contact area.

An electronic device includes a substrate, at least one light-emitting element, at least one first pad and at least one second pad. The light-emitting element is disposed on the substrate and includes a first light-emitting diode, a second light-emitting diode, a conductive layer, an organic layer and an insulation layer. The first light-emitting diode includes a first p-type electrode and a first n-type electrode. The second light-emitting diode includes a second p-type electrode and a second n-type electrode. The first pad and the second pad are respectively disposed on the substrate. The first pad is electrically connected to the first n-type electrode, and the second pad is electrically connected to the second p-type electrode. The conductive layer is electrically connected to the first p-type electrode and the second n-type electrode. One light emitting element only corresponds to one first pad and one second pad.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures with electrical overstress protection are disclosed. LED chip structures are disclosed that include built-in electrical overstress protection. An exemplary LED chip may include an active LED structure that is arranged as a primary light-emitting structure and a separate active LED structure that is arranged as an electrical overstress protection structure. The electrical overstress protection structure may be electrically connected in reverse relative to the primary light-emitting structure. In this manner, under normal operating conditions, forward current will flow through the primary light-emitting structure to generate desired light emissions, and during an electrical overstress event, reverse current may flow through the electrical overstress protection structure, thereby protecting the light-emitting structure from damage.

The forming of the tunnel junction layer includes forming a first n-type layer, forming a second n-type layer by introducing a first raw material gas into a furnace at a first temperature, the first raw material gas including a first gas having a first flow rate, and forming a third n-type layer by introducing a second raw material gas into a furnace at a second temperature, the second raw material gas including a second gas having a second flow rate, the second temperature being less than the first temperature. A first flow rate ratio of the first gas in the first raw material gas is greater than a second flow rate ratio of the second gas in the second raw material gas.

A method for manufacturing a light-emitting element includes: forming a first light-emitting part comprising a first n-type semiconductor layer, a first active layer on the first n-type semiconductor layer, and a first p-type semiconductor layer on the first active layer; forming an intermediate layer on the first light-emitting part; and forming a second light-emitting part on the intermediate layer, the second light-emitting part comprising a second n-type semiconductor layer, a second active layer on the second n-type semiconductor layer, and a second p-type semiconductor layer on the second active layer.

A method of manufacturing a light emitting device including forming first light emitting parts on a first substrate, the first light emitting part including a first n-type semiconductor layer and a first mesa structure including a first active layer, a first p-type semiconductor layer, and a first electrode and exposing a portion of the first n-type semiconductor layer, forming second light emitting parts on a second substrate, the second light emitting part including a second n-type semiconductor layer and a second mesa structure including a second active layer, a second p-type semiconductor layer, and a second electrode and exposing a portion of the second n-type semiconductor layer, attaching a first removable carrier onto the second light emitting parts and enclosing the second light emitting parts, removing the second substrate from the second light emitting parts, and bonding the second light emitting parts to the first light emitting parts.

The present disclosure relates to a method of manufacturing a semiconductor light emitting device, the method comprising: providing a growth substrate on which a first semiconductor region, an active region and a second semiconductor region are sequentially formed; bonding a first light transmitting substrate to the second semiconductor region; removing the growth substrate from the first semiconductor region; attaching a second light transmitting substrate through an adhesive layer to the first semiconductor region from which the growth substrate is removed; laser ablating the first light transmitting substrate from the second semiconductor region; exposing part of the first semiconductor region, and forming a first flip chip electrode and a second flip chip electrode on the exposed first semiconductor region and the exposed second semiconductor region, respectively.

Provided is a solar cell and a photovoltaic module. The solar cell includes a silicon substrate, and the silicon substrate includes a front surface and a back surface arranged opposite to each other. P-type conductive regions and N-type conductive regions are alternately arranged on the back surface of the silicon substrate. Front surface field regions are located on the front surface of the silicon substrate and spaced from each other. The front surface field regions each corresponds to one of the P-type conductive regions or one of the N-type conductive regions. At least one front passivation layer is located on the front surface of the silicon substrate. At least one back passivation layer is located on surfaces of the P-type conductive regions and N-type conductive regions.

A light-emitting element includes, successively from a lower side to an upper side, a first n-side semiconductor layer, a first active layer, a first p-side semiconductor layer, a second n-side semiconductor layer, a second active layer, and a second p-side semiconductor layer, each made of a nitride semiconductor. The second n-side semiconductor layer contacts the first p-side semiconductor layer. The second n-side semiconductor layer includes, successively from a lower side to an upper side, a first layer including gallium, a second layer including aluminum and gallium, and a third layer including gallium and having a lower n-type impurity concentration than the first and second layers. A thickness of the first layer and a thickness of the second layer each is less than 50% of a thickness of the third layer.