Semiconductor Quantum Cascade Lasers (QCLs), in particular mid-IR lasers emitting at wavelengths of about 3-50 μm, are often designed as deep etched buried heterostructure QCLs. The buried heterostructure configuration is favored since the high thermal conductivity of the burying layers, usually of InP, and the low losses guarantee devices high power and high performance. However, if such QCLs are designed for and operated at short wavelengths, a severe disadvantage shows up: the high electric field necessary for such operation drives the operating current partly inside the insulating burying layer. This reduces the current injected into the active region and produces thermal losses, thus degrading performance of the QCL. The invention solves this problem by providing, within the burying layers, effectively designed current blocking or quantum barriers of, e.g. AIAs, InAIAs, InGaAs, InGaAsP, or InGaSb, sandwiched between the usual InP or other burying layers, intrinsic or Fe-doped. These quantum barriers reduce the described negative effect greatly and controllably, resulting in a QCL operating effectively also at short wavelengths and/or in high electric fields.

A semiconductor laser apparatus includes: a semiconductor laser device for junction down mounting that includes a first light-emitting device region and a second light-emitting device region formed separately on a substrate. The first light-emitting device region and the second light-emitting device region in the semiconductor laser device each have a stack structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in stated order. The first light-emitting device region includes a first electrode film located on the n-type semiconductor layer. The second light-emitting device region includes a second electrode film located on the p-type semiconductor layer. The first electrode film and the second electrode film are electrically connected to each other.

The disclosed technology relates to the development of a monolithic active electro-optical device. The electro-optical device may be fabricated using the so-called nanoridge aspect ratio trapping (ART) approach. In one aspect, the disclosed technology is directed to a monolithic integrated electro-optical device, which comprises a III-V-semiconductor-material ridge structure arranged on a Si-based support region. The ridge structure includes a first-conductivity-type bottom region arranged on the support region, a first-conductivity-type lower blocking layer arranged on the top surface and parts of the side surfaces of the bottom region and configured to block second-conductivity-type charge carriers, a not-intentionally-doped (NID) intermediate region arranged on the top and side surfaces of the lower blocking layer and containing a recombination region, a second-conductivity-type upper blocking layer arranged on the top and side surfaces of the intermediate region and configured to block first-conductivity-type charge carriers, and a second-conductivity-type top region arranged on the top and side surfaces of the upper blocking layer.

The disclosed technology relates to the development of a monolithic active electro-optical device. In some embodiments, the electro-optical device may be fabricated using the so-called nanoridge aspect ratio trapping (ART) approach. In one aspect, the electro-optical device is a monolithic integrated electro-optical device comprising a first-conductivity-type Si-based support region and a III-V-semiconductor-material ridge structure extending from the Si-based support region, wherein the ridge structure contains a recombination region. Furthermore, the device comprises a III-V-semiconductor capping layer having a higher band-gap than that of the III-V semiconductor material of the ridge structure and being formed on an outer surface of the ridge structure. The device further comprises at least one second-conductivity-type III-V-semiconductor fin structure narrower than and extending upwards from a top surface of the ridge structure through an opening in the capping layer on the top surface of the ridge structure.

A semiconductor laser includes an active layer which is provided between the p-type semiconductor region and the n-type semiconductor region and has a type II quantum well structure. The type II quantum well structure includes a well layer made of a III-V compound semiconductor and a plurality of barrier layers. The well layer includes a first region and a second region, the first region having a low potential for electrons in the well layer and a high potential for holes in the well layer, the second region having a high potential for electrons in the well layer and a low potential for holes in the well layer. The first region and the second region of the well layer are arranged in a direction from one of the barrier layers to another of the barrier layers.

Semiconductor Quantum Cascade Lasers (QCLs), in particular mid-IR lasers emitting at wavelengths of about 3-50 m, are often designed as deep etched buried heterostructure QCLs. The buried heterostructure configuration is favored since the high thermal conductivity of the burying layers, usually of InP, and the low losses guarantee devices high power and high performance. However, if such QCLs are designed for and operated at short wavelengths, a severe disadvantage shows up: the high electric field necessary for such operation drives the operating current partly inside the insulating burying layer. This reduces the current injected into the active region and produces thermal losses, thus degrading performance of the QCL. The invention solves this problem by providing, within the burying layers, effectively designed current blocking or quantum barriers of, e.g. AIAs, InAIAs, InGaAs, InGaAsP, or InGaSb, sandwiched between the usual InP or other burying layers, intrinsic or Fe-doped. These quantum barriers reduce the described negative effect greatly and controllably, resulting in a QCL operating effectively also at short wavelengths and/or in high electric fields.

The semiconductor laser including a substrate, and a p-type electron overflow prevention layer between an active layer and a p-type cladding layer further includes a p-type strained layer (p-type Al.sub.zIn.sub.1-zAs layer, where z>x), having a large band gap, between the p-type electron overflow prevention layer (p-type Al.sub.xIn.sub.1-xAs layer) and p-type cladding layer. The provision of the p-type strained layer (p-type Al.sub.zIn.sub.1-zAs layer) reduces the heights of heterojunction spikes on a valence band, thereby lowering a barrier over which holes are injected into the active layer, and resultantly reducing the resistance in the elements and reducing heat generation in the semiconductor laser. In addition, a conduction band barrier (Ec) is raised in the energy band, thereby effectively preventing electron overflow. Thus, the semiconductor laser characteristics are improved.

A semiconductor laser apparatus includes: a semiconductor laser device for junction down mounting that includes a first light-emitting device region and a second light-emitting device region formed separately on a substrate. The first light-emitting device region and the second light-emitting device region in the semiconductor laser device each have a stack structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in stated order. The first light-emitting device region includes a first electrode film located on the n-type semiconductor layer. The second light-emitting device region includes a second electrode film located on the p-type semiconductor layer. The first electrode film and the second electrode film are electrically connected to each other.

A method for producing an integrated optical circuit comprising an active device and a passive waveguide circuit includes: applying an active waveguide structure on a source wafer substrate; exposing a portion of the source wafer substrate by selectively removing the active waveguide structure; applying a passive waveguide structure on the exposed portion of the source wafer substrate, wherein an aggregation of the active waveguide structure and the passive waveguide structure forms the active device, the active device having a bottom surface facing the source wafer substrate; removing the source wafer substrate from the active device; and attaching the active device to a target substrate comprising the passive waveguide circuit such that the bottom surface of the active device faces the target substrate.