An embodiment converter includes a magnetic material, a first circuit including a first winding surrounding the magnetic material and a clamp circuit configured to reset a power conversion operation, the first circuit being configured to convert power received from a first input voltage source to provide the converted power to a load, and a second circuit including a second winding surrounding the magnetic material, the second circuit being configured to convert power received from a second input voltage source to provide the converted power to the load and to perform the power conversion operation being reset by the clamp circuit.

A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

A voltage regulator with dynamic voltage and frequency tracking is shown. The voltage regulator has power switches converting an input voltage into an output voltage, a control loop, a voltage comparator, and a target voltage generator. The control loop is coupled to the power switches to control the power switches to perform voltage regulation. The voltage comparator compares the output voltage to the target voltage to generate a first control signal to control the control loop. The target voltage generator generates the target voltage for the voltage comparator based on the frequency difference between the target frequency and the critical-path-related frequency, wherein the critical-path-related frequency depends on the output voltage. The power efficiency and response time are improved.

A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.

This present invention is an invented synchronous clock generator for the multiphase DC-DC converter system, comprising a front-end buffer circuit, a ramp signal generator circuit, a configurable equally divided reference voltage generator circuit, a set of comparators, a 10-ns pulse generator, multiple 30-ns pulse generators, and a pulse combination circuit. The synchronous clock generator can produce a clock pulse signal SYNC at N (total phase number) times the single-phase switching frequency. Within one synchronous loop period, a 10-ns pulse is first generated and followed by N-1 30-ns pulses. The master power stage chip detects the 10-ns pulse, and all the slave power stages detect and count the 30-ns pulses to determine when to set their output signal PWM. Thus, the invention can produce the new SYNC signal immediately with balanced phase shift while allowing the changing of the total phase number N by the total phase number register.

A wireless power receiver includes a rectifier configured to convert a radio frequency (RF) voltage signal generated based on an RF input to a direct current (DC) voltage, and a boost converter configured to generate a voltage for battery charging using the RF voltage signal as a switching signal.

An electronic device has a modulator circuit, a pulse adjustment circuit, and a pulse generator circuit. The modulator circuit generates a comparator output signal based on a sensed inductor current signal of a power converter, an error amplifier output voltage signal, and a ramp signal to regulate an output voltage signal of the power converter. The pulse adjustment circuit generates an adjusted pulse signal based on the comparator output signal and the error amplifier output voltage signal, and to generate an adjusted clock signal based on an input clock signal and the error amplifier output voltage signal. The pulse generator circuit generates a switching control signal to control a transistor of the power converter based on the adjusted pulse signal and the adjusted clock signal.

The present disclosure provides a switching current source circuit and a method for quickly establishing a switching current source. The switching current source circuit includes a first and a second switching current source branches connected in parallel with one end of a load. When the switching enable signal is switched, due to the charge coupling of the first and second switching current source branches, the bias voltage respectively generates bounce in the same direction as and a direction opposite to the transition direction of the switching enable signal. The two bounces cancel each other to make the current source bias voltage recover quickly when a toggle event happens. The present disclosure accelerates the establishment of current through the coupling of charges, and reduces the decoupling capacitance at the same time, thereby reducing the circuit area and saving the costs.

A power converter circuit included in a computer system may include multiple devices and a switch node coupled to a regulated power supply node via an inductor. During a first time period, the power converter charges a capacitor, and the couples the capacitor to the switch node during a second time period. During a third time period the power converter couples the switch node to an input power supply node. To maintain constant charge delivered to the load during each time the switch node is coupled to the input power supply node, the duration of the third time period is adjusted based on a voltage level of the input power supply node, a voltage level of the regulated power supply node, a value of the inductor, and the durations of first and second time periods.

This present invention is an invented synchronous clock generator for the multiphase DC-DC converter system, comprising a front-end buffer circuit, a ramp signal generator circuit, a configurable equally divided reference voltage generator circuit, a set of comparators, a 10-ns pulse generator, multiple 30-ns pulse generators, and a pulse combination circuit. The synchronous clock generator can produce a clock pulse signal SYNC at N (total phase number) times the single-phase switching frequency. Within one synchronous loop period, a 10-ns pulse is first generated and followed by N-1 30-ns pulses. The master power stage chip detects the 10-ns pulse, and all the slave power stages detect and count the 30-ns pulses to determine when to set their output signal PWM. Thus, the invention can produce the new SYNC signal immediately with balanced phase shift while allowing the changing of the total phase number N by the total phase number register.