The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electronic components and compatible with traditional integrated circuit technologies. Each LC oscillator, or node, in the network can be coupled to each other node in the array with a multiply and accumulate crossbar array or optical interconnects. When implemented with four nodes, the system performs with single-run ground state accuracies of 98% on randomized MAX-CUT problem sets with binary weights and 84% with five-bit weight resolutions. The four-node system can obtain solutions within five oscillator cycles with a time-to-solution that scales directly with oscillator frequency. A scaling analysis suggests that larger coupled oscillator networks may be used to solve computationally intensive problems faster and more efficiently than conventional algorithms.

An inductive switch comprises an inductor that has a primary metallic winding having a boundary configured in shape of a figure eight, such as in two loops, and a plurality of secondary metallic windings arranged within the boundary of the primary metallic winding. The inductive switch includes a plurality of switches, each switch arranged in series with a respective one of the plurality of secondary metallic windings. An equal number of the secondary windings is arranged within each loop. A tunable inductor comprises at least one main metallic loop and at least one secondary metallic loop, wherein the at least one secondary metallic loop comprises a switch that is arranged to configure the at least one secondary metallic loop into at least one shorted metallic loop or at least one closed metallic loop. The at least one shorted loop is floating.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

A method for detecting an RF signal detected by a super-regenerative receiver (1). The receiver includes a reference oscillator (4) for generating an oscillation in the oscillator, a bias current generator (7) for supplying a bias current, an oscillation detector (6) connected between an output (coilp) of the oscillator and the bias current generator for controlling when an RF signal is received by the receiver, and an impedance matching unit (3) disposed between the input of the receiver and the reference oscillator (4). Following activation of a start control signal, detection of the oscillation of the reference oscillator is performed, and once the reference oscillator oscillates above a critical increasing bias current value, the oscillation detector orders the bias current generator to cut off the bias current and thus stop the oscillation of the reference oscillator to reduce the overall electricity consumption during an RF signal detection phase.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

A DC-DC converter includes: an transformer having a primary winding and a secondary winding magnetically coupled to the primary winding; a power oscillator applying an oscillating signal to the primary to transmit a power signal to the secondary winding; a rectifier connected to the secondary winding of the transformer to obtain an output DC voltage by rectification of the power signal; comparison circuitry to generate an error signal representing a difference between the output DC voltage and a reference voltage; a transmitter connected to the secondary winding of the transformer to apply an amplitude modulation to the power signal at the secondary winding of the transformer in response to the error signal to thereby produce an amplitude modulated signal at the primary winding; and a receiver and control circuit connected to the primary winding to control an amplitude of the oscillating signal as a function of the amplitude modulated signal.

The smart window for the smart home and smart grid can harvest energy and supply power to the home, grid and window itself. The smart window for the smart home and smart grid has all the Electrochromic panel, Solar panel and Multimedia panel been the same full window wide view and aligned with each other in IGU. To be a home automation system, the smart window has local/remote access/control capabilities. There are several types of smart windows working as master device or slave device. The operation of smart window automation system has three modes, normal/open mode, shut/tint mode and smart phone mode. The tube of air circulation system is hidden inside the frame surrounding IGU. Most of the electronic components are integrated to be FPSOC Field Programmable System On Chip that all the electronic component is hidden in the frame surrounding IGU, too. Therefore, the smart window doesn't have any blockage of window view with the Solar panel, Electrochromic panel, Multimedia panel and air circulation system. The smart window has the clean outlook as the conventional dual panel IGU does. The master device of the smart window system is similar to the huge screen working as a smart phone. In normal/open mode, the smart window is similar to the conventional dual panel window having the full-panel clean and clear view. For the different architectures of the smart homes, the smart window must have versatile alignments and system control that the smart window has to be implemented with the Field Programmable System On Chips of Anlinx, Milinx and Zilinx made of the W5RS advanced FPSOC chip technologies.

A voltage controlled oscillator includes a series resonant circuit having a resonance frequency and an active voltage driving device coupled to the series resonant circuit. The active voltage driving device provides a driving voltage and has an output negative resistance in an operative voltage range at the resonance frequency. The active voltage driving device includes a cross-coupled differential pair having voltage supply terminals providing the driving voltage. The series resonant circuit is coupled between the voltage supply terminals of the cross-coupled differential pair.