The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

Cross-coupled structures are provided. Cross-coupled structures may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor, the second transistor, and the fourth transistor may be spaced apart from each other in a first direction, and the third transistor and the second transistor may be stacked in a second direction that is perpendicular to the first direction. The third transistor and the second transistor may include a common gate structure, a first portion of the common gate structure may be a gate structure of the second transistor, and a second portion of the common gate structure may be a gate structure of the third transistor.

A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.

There is provided a power supply device configured to boost an input voltage to output an output voltage, the power supply device including: an oscillator circuit configured to receive the input voltage and to output an oscillation signal; a step-up circuit configured to output a boost voltage based on the oscillation signal; a first hysteresis comparator and a second hysteresis comparator configured to compare boost voltages with threshold values; a first switch that is connected between the oscillator circuit and the step-up circuit and that is controlled based on a comparison result of the first hysteresis comparator; and a second switch that is connected to an output terminal configured to output the output voltage and that is controlled based on a comparison result of the second hysteresis comparator.

An integrated circuit includes an oscillator and a power amplifier. The oscillator includes a first node, a second node, and a network of one or more reactive components coupled between the first node and the second node. The power amplifier includes a first input coupled to the first output of the oscillator, a second input coupled to the second output of the oscillator, and an output. The power amplifier includes a coarse gain control circuit, a first amplifier stage, and a second amplifier stage.

A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount Φ in a first variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount Φ in a second variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electronic components and compatible with traditional integrated circuit technologies. Each LC oscillator, or node, in the network can be coupled to each other node in the array with a multiply and accumulate crossbar array or optical interconnects. When implemented with four nodes, the system performs with single-run ground state accuracies of 98% on randomized MAX-CUT problem sets with binary weights and 84% with five-bit weight resolutions. The four-node system can obtain solutions within five oscillator cycles with a time-to-solution that scales directly with oscillator frequency. A scaling analysis suggests that larger coupled oscillator networks may be used to solve computationally intensive problems faster and more efficiently than conventional algorithms.

An inductive switch comprises an inductor that has a primary metallic winding having a boundary configured in shape of a figure eight, such as in two loops, and a plurality of secondary metallic windings arranged within the boundary of the primary metallic winding. The inductive switch includes a plurality of switches, each switch arranged in series with a respective one of the plurality of secondary metallic windings. An equal number of the secondary windings is arranged within each loop. A tunable inductor comprises at least one main metallic loop and at least one secondary metallic loop, wherein the at least one secondary metallic loop comprises a switch that is arranged to configure the at least one secondary metallic loop into at least one shorted metallic loop or at least one closed metallic loop. The at least one shorted loop is floating.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.