A current source and/or current sink digital-to-analog converter (DAC) includes a DAC circuit that converts a digital code to an analog current or voltage signal, an optional transconductance circuit that converts a voltage output of the DAC circuit into a current signal, and an output circuit that amplifies a current output of the DAC circuit or optionally amplifies a current output of the transconductance circuit to set a desired high current output for application to an output of the current source and/or current sink DAC. A power supply control current may be coupled to a power supply circuit that supplies power to the output circuit of the current source and/or current sink DAC. The power supply control current adjusts the output of the power supply circuit to cause the current source and/or current sink DAC to operate at a higher power efficiency.

A DC-to-DC voltage regulator circuit comprising: an output node; a pull-up switch and a pull-down switch with an output node coupled between them; a reactive circuit element coupled to the output node; a pull-up setting voltage circuit coupled to provide a pull-up setting voltage that is a function of a voltage at the output node; a pull-down setting voltage circuit coupled to provide a pull-down setting voltage that is a function of the voltage at the output node; a first comparator coupled to cause the pull-up switch to transition between open switch state and its closed switch state based upon a comparison of the pull-up setting voltage and a control voltage; and a second comparator coupled to cause the pull-down switch to transition between its open switch state and its closed switch state.

A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.

An apparatus and method for calibrating an envelope tracking (ET) lookup table (LUT) are provided. An ET power management apparatus includes a power amplifier configured to amplify a radio frequency (RF) signal from a time-variant input power to a time-variant output power linearly related to the time-variant input power. A calibration circuit is employed to receive a time-variant output power feedback nonlinearly related to the time-variant input power, determine a linear relationship between the time-variant input power and the time-variant output power based on the time-variant output power feedback, and calibrate the ET LUT based on the determined linear relationship. As a result, it is possible to improve accuracy of the ET LUT to thereby improve operating efficiency and linearity of the power amplifier.

The present invention is in the field of booster stage circuit for a power amplifier, and an external supply voltage power amplifier comprising said booster stage circuit, such as for amplifying an electronic signal to a speaker system. These amplifiers may be provided with an external supply voltage.

A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

Power supplies for electronic devices (e.g. medical imaging devices) are disclosed herein. In one embodiment, a switched mode power supply is minimized in size and weight while maintaining efficiency and an artifact-free image using power supply design techniques tailored to increasing the power conversion frequency to be above the desired receive band of an ultrasound imaging system. In another embodiment, a switched mode power supply is minimized in size and weight while maintaining efficiency and an artifact-free image using power supply design techniques tailored to increasing the power conversion frequency to be just below the desired receive band of an ultrasound imaging system causing the third harmonic and possibly the second harmonic to fall just above the desired receive band.

A tracking power supply includes a power conversion subsystem and one or more tracking subsystems. The power conversion subsystem is configured to generate N power rails, where N is an integer greater than one. Each tracking subsystem includes a switching network and a controller. The switching network is electrically coupled between each of the N power rails and a tracking power rail of the tracking power supply. The controller is configured to control operation of the switching network according to a tracking signal associated with a load powered by the tracking power supply, such that a voltage at the tracking power rail is one of two or more values, as determined at least partially based on the tracking signal. The controller is further configured to adjust voltage of at least one of the N power rails.

A power detector device includes a power detector circuit, a filter circuit, and a calibration circuitry. The power detector circuit is configured to detect a first signal to generate a second signal. The filter circuit is configured to filter the second signal to generate a third signal. The calibration circuitry is configured to determine first signal strength information in response to the third signal, adjust a gain of the power detector circuit to obtain second signal strength information, and combine the first signal strength information and the second signal strength information, in order to calibrate a detection power range of the power detector circuit to be linear.

A current flowing through a transistor of a final-stage amplifier is suppressed. A power amplification circuit includes a driving-stage amplifier, a final-stage amplifier, a power supply terminal, a first voltage control circuit, and a second voltage control circuit. The driving-stage amplifier includes a first transistor having a first input terminal, a first output terminal, and a first ground terminal. The final-stage amplifier includes a second transistor having a second input terminal, a second output terminal, and a second ground terminal. The first voltage control circuit is connected between the power supply terminal and the first output terminal, and controls a first power supply voltage applied to the first transistor. The second voltage control circuit is connected between the power supply terminal and the second output terminal, and controls a second power supply voltage applied to the second transistor.