A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

A method and a device for amplifying an input signal include a power amplifier for amplifying a binary input signal, a modulation device for generating the binary input signal on the basis of the input signal, the input signal being a complex-valued signal and the binary input signal being a real-valued signal, the modulation device including an adding device configured to add the complex-valued input signal to a complex-valued carrier signal of a predefined frequency and to thus generate a resulting complex-valued signal, and the modulation device including a combination device connected downstream from the adding device and configured to generate the real-valued binary input signal from the real part and the imaginary part of the resulting complex-valued signal by combining the real part and the imaginary part of the resulting complex-valued signal.

To suppress voltage variations due to transistor switching noise in a solid-state image sensor including a transistor that initializes a differentiating circuit. A capacitance supplies a charge corresponding to an amount of variation in a predetermined pixel voltage to a predetermined input terminal. A voltage output unit outputs, as an output voltage, a voltage corresponding to an input voltage at the input terminal from a predetermined output terminal. A reset transistor supplies one of a positive charge or a negative charge during a predetermined period to control the output voltage to an initial value in a case where initialization is instructed. A charge supply unit supplies the other of the positive charge or the negative charge when the predetermined period elapses.

An amplifier circuit includes a resistor divider (R.sub.REF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d.sub.1, d.sub.2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I.sub.REF) connected or connectable to the first main node (a). The resistor divider (R.sub.REF) comprises two arrays of addressable switch elements controllable by a feedback signal (s.sub.FB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T.sub.1, T.sub.2), wherein source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b), gate terminals of the transistors (T.sub.1, T.sub.2) are connected to input signals (v.sub.1, v.sub.2), drain terminals of the transistors (T.sub.1, T.sub.2) are connected to current sources (I.sub.1, I.sub.2), and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the readout nodes (d.sub.1, d.sub.2). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

An RF amplifier comprises a first ‘transconductance’ transistor (N.sub.CS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (N.sub.CG) has its source terminal connected to the drain terminal of the first transistor (N.sub.CS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (V.sub.BCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (V.sub.BCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (N.sub.CG).

According to one aspect, an integrated circuit includes a power amplifier having a succession of at least two amplifier stages. The two amplifier stages include a first amplifier stage configured to receive a radio frequency signal as input and a last amplifier stage configured to deliver as an output of an amplified radio frequency signal. The power amplifier further includes a safety circuit with a control circuit configured to compare the amplified radio frequency signal voltage with a threshold voltage. The safety circuit further comprises a gain reduction circuit configured to reduce a bias voltage of an upstream amplifier stage of the last amplifier stage when the amplified radio frequency signal voltage is greater than the threshold voltage.

A radio-frequency circuit includes an amplifier circuit, a bias circuit, a bias control circuit, a comparing section, a signal input terminal, an antenna terminal, an attenuation circuit, and a control unit. The amplifier circuit includes a specific transistor. The bias circuit supplies a bias current or a bias voltage to the input terminal of the specific transistor. The bias control circuit supplies a control current or a control voltage to the bias circuit. The comparing section compares a threshold voltage with a power supply voltage of a power supply terminal connected to the output terminal of the specific transistor. The attenuation circuit is connected in a signal path between the signal input terminal and the antenna terminal and is capable of attenuating the radio-frequency signal. The control unit changes an attenuation of the attenuation circuit in accordance with a compared result of the comparing section.

A radio-frequency circuit includes an amplifier circuit, a bias circuit, a bias control circuit, a comparing section, a variable resistance circuit, and a control unit. The amplifier circuit includes a transistor that amplifies a radio-frequency signal input to an input terminal and outputs the radio-frequency signal from an output terminal. The bias circuit supplies a bias current or a bias voltage to the input terminal of the transistor. The comparing section compares a threshold voltage with a power supply voltage of a power supply terminal connected to the output terminal of the transistor. The variable resistance circuit is connected between the power supply terminal and the output terminal. The variable resistance circuit includes a parallel circuit made up of a resistive element and a switch element. The control unit changes a resistance value of the variable resistance circuit in accordance with a compared result of the comparing section.

The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.