A class D amplifier including a pulse width modulation (PWM) control loop, an H-bridge driver, a PWM controller having a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by an analog-to-digital converter of the PWM control loop, and a comparator. The comparator is configured to trigger a cutoff of a PWM pulse generated by the PWM pulse generator during a respective loop cycle of the PWM control loop and to trigger generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.

In some embodiments, an audio amplifier can include an input node for receiving a digital signal, and a controller coupled to the input node through a feed-forward path. The controller can be configured to generate a driving signal based on the digital signal. The audio amplifier can further include a driver configured to provide an amplified signal at an output node based on the driving signal, and a feedback circuit that couples the output node of the driver to the controller. The feedback circuit can be configured to provide a feedback signal for comparison with a reference signal representative of the digital signal to generate an error signal, such that the feedback circuit provides a form of the error signal to the controller for adjustment of the digital signal.

A switching audio amplifier and method of operation. The switching audio amplifier comprises a voltage supply selector coupling a power supply input to a first power supply voltage; a switching circuit generating a drive signal for a loudspeaker by modulating the power supply input based on a modulation signal; a pulse generator receiving an audio input signal and outputting the modulation signal based on the audio input signal and the voltage of the power supply input; and a supply voltage monitor. The supply voltage monitor is configured to increase the voltage of the power supply input by causing the voltage supply selector to couple the power supply input to a second power supply voltage responsive to the modulation signal exceeding the first threshold, and the supply voltage monitor preventing the voltage supply selector from reducing the voltage of the power supply input for a first time period.

In some embodiments, an audio driver includes an audio amplifier configured to operate in a high output resistance (HOR) mode with an HOR driver or a zero output resistance (ZOR) mode with a ZOR driver, The audio amplifier includes an output node coupled to both of the HOR driver and the ZOR driver, such that the output node is subject to an effect of the ZOR driver in a disabled state when the audio amplifier is operating in the HOR mode. The audio driver further includes a control system configured to correct for the effect of the disabled ZOR driver by adjusting an input signal.

A series-connected delta-sigma modulator (DSM) comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal, and to feed back the first quantized signal to the first loop filter, wherein the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal, and to feed back the second quantized signal to the second loop filter, wherein the second quantized signal comprises a quantization error smaller than a second predetermined value.

A differential delta-sigma-modulator has an integrator including a pair of single-ended amplifiers. A sample clock is driving a first switchable capacitor configuration and a second switchable capacitor configuration at a predetermined switching cycle. The first switchable capacitor configuration is adapted for sampling respective outputs from the pair of single-ended amplifiers on a pair of output sampling capacitors in the first part of the switching cycle. The second switchable capacitor configuration is adapted for charging a common mode capacitor with the average voltage of the voltage sampled by the pair of output sampling capacitors in the second part of the switching cycle. The voltage across the common mode capacitor represents the common mode voltage for the integrator.

The present invention discloses an audio processing circuit, wherein when the audio processing circuit determines that a signal being processed is a small signal, an output stage uses a regulated supply voltage provided by a voltage regulator, and the output stage uses an open-loop structure to reduce noise of an output audio signal; and when the audio processing circuit determines that the signal being processed is a large signal, the output stage directly uses the supply voltage without using the regulated supply voltage, and the output stage uses a closed-loop structure to reduce the total harmonic distortion of the output audio signal. By using the present invention, the audio processing circuit can have a good performance indicator with a small chip area design.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

The present invention provides an offset calibration circuit used in a signal processing circuit, wherein the offset calibration circuit includes a supply voltage detection circuit and a calibration circuit. The supply voltage detection circuit is configured to detect a level of a supply voltage to generate a detection result, wherein the supply voltage is provided to an output stage in the signal processing circuit. The calibration circuit is configured to calculate a digital compensation value according to the detection result, wherein the digital compensation value is used for a digital processing circuit in the signal processing circuit to perform a DC offset calibration.

A high-order converter generates a first high-order voltage V.sub.U_P and a second high-order voltage V.sub.U_N that monotonously change with mutually opposite polarities with respect to high-order m bits (1≤m<n) of the digital signal. A low-order converter generates a first low-order voltage and a second low-order voltage that monotonously change with mutually opposite polarities with respect to low-order (n−m) bits of the digital signal. A first amplifier receives one of the first and the second high-order voltages and one of the first and the second low-order voltages to output one differential analog signal. Having a configuration in common with the first amplifier, a second amplifier receives another of the first and the second high-order voltages and another of the first and the second low-order voltages to output another differential analog signal.