In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

A dual-band MMIC power amplifier and method of operation to amplify frequencies in different RF bands while only requiring input drive signals at frequencies f.sub.1 and f.sub.2 in a narrow RF input band. This allows for the use of a conventional narrowband RF IC to drive the MMIC and does not require additional circuitry (e.g., a LO) on the MMIC power amplifier. The matching network of the last amplification stage is modified to pass f.sub.1 (or a harmonic thereof), reflect f.sub.2, pass a P.sup.th harmonic of f.sub.2 where P is 2 or 3 and to reflect any unused 1.sup.st, 2.sup.nd or 3.sup.rd order harmonics of f.sub.1 or f.sub.2 back into the MMIC. In response to an input signal at f.sub.1, the MMIC power amplifier amplifies and outputs a signal at f.sub.1 (or a harmonic thereof). In response to an input signal at f.sub.2 at sufficient RF power, the last amplification stage operates in compression such that the MMIC power amplifier generates the harmonics, selects the P.sup.th harmonic and outputs an amplified RF signal at P*f.sub.2.

An activation circuit which can realize both of area reduction and current consumption reduction by more preferred embodiments. The activation circuit has an N-type MOS transistor having a gate terminal connected to a ground and having a threshold voltage in a vicinity of 0 V and a resistor interposed between a source terminal of the MOS transistor and a ground, wherein an electric potential of a drain terminal of the MOS transistor is controlled depending on a first signal output from a device serving as a drive target, and transmission of a second signal for activating the device is controlled depending on the electric potential of the drain terminal.

A circuit for converting a first voltage to a second voltage in a communication system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.

Provided is an amplifier that includes a first transistor including a gate terminal to which an applied input signal is input, where a current depending on the applied input signal flows through the first transistor. A gate terminal of a second transistor is connected to a load section, and a current depending on a change in a voltage of the drain terminal of the first transistor flows through the second transistor. A source terminal of the first transistor and a drain terminal of the second transistor are connected in common to a first resistance, and the current from the first transistor and the current from the second transistor flow through the first resistance. A third transistor supplies a current approximately equal to the current of the second transistor. The current supplied by the third transistor is output from an output end.

An amplifier circuit according to an embodiment includes a first circuit, a second circuit, and a third circuit. The first circuit includes a first transistor connected between an input node through which an input current flows and a reference potential node. The first transistor has a gate electrode connected to the input node. The second circuit includes a low-pass filter circuit and a second transistor connected in parallel to the first transistor between the input node and the reference potential node. The second transistor has a gate electrode connected to the gate electrode of the first transistor via the low-pass filter circuit. The third circuit includes a third transistor connected between an output node through which an output current flows and the reference potential node, the third circuit having a gate electrode connected to the gate electrode of the first transistor.

An overcurrent protection circuit includes: a first transistor and a second transistor configured to form an amplifier input stage that receives input of a detection signal according to a monitoring target current; and a third transistor configured to form an amplifier output stage that generates a current output signal according to a difference between the detection signal and a reference signal and causes the current output signal to be negatively fed back to the amplifier input stage, wherein the monitoring target current is limited based on the current output signal output from the third transistor.

According to one embodiment, a constant voltage circuit includes: a first gain stage configured to output a first voltage amplified based on an output voltage and a reference voltage; a first transistor configured to control the output voltage based on the first voltage; a second transistor configured to control a current that flows through the first gain stage; a first circuit configured to convert an amount of fluctuation in the output voltage into a first current; and a second circuit configured to control a gate voltage of the second transistor based on the first current. A third current or a fourth current greater than the third current flows through the first gain stage based on the gate voltage of the second transistor.

A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.