Patent classifications
H03F3/423
STABILIZED NON-INDUCTIVE VOLTAGE BOOST CONVERTER OPERATING AT MOS SUB-THRESHOLD VOLTAGE FROM ANALAGOUS MICROPOWER PYROELECTRIC DEVICE
Disclosed herein is a non-Inductive voltage boost-converter (NVBC) for micro-power energy harvesting systems for energy storage and delivery applications. Current devices deliver a wide-range of micro-power having only up to 0.8V peak-voltage, but nominally 0.45V in lab test conditions. This voltage is not adequate in charging storage cells such as rechargeable batteries and also driving electronic circuits. Technology is in demand where a boost-converter must operate at MOS sub-threshold voltage (Sub-V.sub.TH) limits. Disclosed herein is a novel NVBC device that has eliminated the need of an inductor coil and associated high-speed switching circuits; thus achieving higher efficiency. The disclosed invention applies a simple self-synchronizing technique to adapt the NVBC automatically to the low-frequency energy signal of a pyroelectric device. A novel NVBC is presented for stabilized output of NVBC (S-NVBC). In an embodiment, the S-NVBC achieves an efficiency of 86%.
SINGLE STRUCTURE CASCODE DEVICE AND METHOD OF MANUFACTURING SAME
Disclosed in a CASCODE device in which multiple transistors are stacked in a vertical direction and connected in series. The CASCODE device exhibits improvements in device/circuit intrinsic gain (GmRo) that is a performance index for analog/RF applications, cutoff frequency (Ft), and maximum oscillation frequency (Fmax). A method of manufacturing the CASCODE device is also disclosed.
SEMICONDUCTOR DEVICES HAVING A PLURALITY OF UNIT CELL TRANSISTORS THAT HAVE SMOOTHED TURN-ON BEHAVIOR AND IMPROVED LINEARITY
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
POWER AMPLIFIER AND METHOD OF OPERATING THE POWER AMPLIFIER
A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.
Power amplifier and method of operating the power amplifier
A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.
Oscillator circuit using comparator
An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.
Self-biased amplifier for use with a low-power crystal oscillator
A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.
Optoelectronics integration using semiconductor on insulator substrate
A III-V optoelectronic light emitting device is epitaxially formed on a semiconductor on insulator substrate over a buried waveguide core. The device is optically coupled to the underlying waveguide core. A MOSFET device is formed on a semiconductor substrate beneath the insulator that contains the waveguide core.
Self-Biased Amplifier for Use with a Low-Power Crystal Oscillator
A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.