An amplifier circuit has an output stage, a first current source, a second current source, a third current source, a fourth current source, and a voltage clamping voltage. The output stage has a first P-type transistor and a first N-type transistor. The voltage clamping circuit receives a first bias voltage and a second bias voltage, and has a first end and a second end. When a second input current is positive current and the input current is a negative current or a zero current, the first end provides a first clamping voltage greater than the first bias voltage to a gate of the first P-type transistor. When the first input current is positive and the second input current is a negative current or zero current, the second end provides a second clamping voltage lower than the second bias voltage to a gate of the first N-type transistor.

An operational amplifier compensation circuit includes; a first transistor activated/deactivated in response to a signal level difference between an input signal applied to an operational amplifier and an output signal provided by the operational amplifier, a first signal amplifying circuit including a second transistor and a first load, wherein the first signal amplifying circuit is configured to generate a first gate voltage amplified in response to the voltage level difference between the input signal and the output signal in relation to an internal resistance of the second transistor and a resistance of the first load when the first transistor is activated, and a third transistor configured to generate a first compensation current in response to the amplified first gate voltage and provide the first compensation current to the operational amplifier.

An exemplary embodiment of the present disclosure relates to a rail-to-rail class-AB buffer amplifier using compact adaptive biasing, and the rail-to-rail class-AB buffer amplifier using compact adaptive biasing includes an input stage generating a differential current pair based on a voltage difference between a first input signal and a second input signal, an amplification stage outputting a driving signal based on the differential current pair, an output stage connected to the amplification stage and outputting an output signal, an auxiliary current source switch which is on/off based on the driving signal of the amplification stage, and a current mirroring unit generating bias current and outputting the generated bias current to the input stage when the auxiliary current source switch is on.

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

An output buffer circuit includes an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and on a compensation current, a slew rate compensating circuit configured to generate the compensation current to increase a slew rate of the amplifier output voltage signal based on a difference between the input voltage signal and a feedback voltage signal, an output path circuit connected between the operational amplifier and an output pad, the output path circuit configured to transfer the amplifier output voltage signal to generate a pad output voltage signal through the output pad, and a feedback path circuit, the feedback path circuit connected between the slew rate compensating circuit and a feedback input node that is on the output path circuit, the feedback path circuit configured to generate the feedback voltage signal.

A differential amplifier which does not have an effect of noise resistance deterioration, waveform distortion, and a lower bandwidth while having a wide input range is realized. The differential amplifier does not cause deterioration in a signal quality due to an increase in an input load, and it is not necessary to additionally provide a configuration for generating a reference voltage. The differential amplifier includes a differential amplification circuit and an output circuit for amplifying and outputting a differential output from the differential amplification circuit. The differential amplification circuit includes a first conductive type first differential pair which supplies output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a second conductive type second differential pair which supplies output currents according to a positive phase input signal and a reverse phase input signal to the output circuit, a detector which detects an operation state of a differential pair, and an alternative current supplying circuit which supplies an alternative current for the output current of the differential pair which has been turned off to the output circuit.

A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.

An apparatus comprises a digital to analog converter (DAC) circuit configured to receive a time-varying a digital input signal and convert the digital input signal to an analog output signal, an output amplifier circuit operatively coupled to the output of the DAC circuit, a peak detector circuit operatively coupled to the input the DAC and configured to produce a signal envelope of the digital input signal, and logic circuitry. The logic circuitry is operatively coupled to the peak detector circuit and is configured to detect when the signal envelope satisfies a specified threshold value; and to adjust a drive capability of an output amplifier circuit of the DAC circuit according to the signal envelope.

Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.