In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

A charge-steering amplifier circuit and a control method thereof are provided. The charge-steering amplifier circuit is used for amplifying a differential input signal and includes a sample-and-hold circuit, a charge-steering amplifier, a reference voltage generation circuit, and a switch circuit. The sample-and-hold circuit is configured to sample the differential input signal to generate first and second sampled signals. The charge-steering amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first and second input terminals receive the first and second sampled signals, respectively. The reference voltage generation circuit is configured to generate a reference voltage according to the differential input signal. The switch circuit is configured to couple the reference voltage to the first output terminal and the second output terminal.

A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.

A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

A differential amplifier circuit of the present invention includes a differential input circuit including first and second transistors, and amplifies a difference voltage between a first input voltage applied to a control terminal of the first transistor and a second input voltage applied to a control terminal of the second transistor. The differential input circuit a P-channel depletion type transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and the P-channel depletion type transistor operates as a bias current source of the differential amplifier circuit.

An amplifier may include multiple transistors with two transistors having their gates tied together via a common connection. The amplifier may utilize a local common mode feedback resistor as part of the amplifier. The local common mode feedback resistor may be coupled between the common connection and respective terminals of two transistors of multiple transistors. The local common mode feedback resistor may include a group of resistors coupled in series. The local common mode feedback resistor may also include a metal oxide semiconductor (MOS) resistor coupled in parallel with one or more of the first group of resistors. In the local common mode feedback, the first MOS resistor provides different levels of resistance to different process corners to reduce overshoot when the amplifier is enabled.

An amplifier and an electronic system including the same are provided. An amplifier includes a first NMOS transistor configured to receive a first input, a second NMOS transistor configured to receive a second input, the second NMOS transistor including a source connected to a source of the first NMOS transistor, a first resistor including a first end connected to a drain of the first NMOS transistor and a second end connected to a first output, a second resistor including a first end connected to a drain of the second NMOS transistor, and a second end connected to a second output, and the amplifier is configured to generate the first output and the second output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor.

A semiconductor device includes a semiconductor chip that has a main surface, a device region that is demarcated at the main surface, a differential amplifier that is formed in the device region and that amplifies and outputs a differential signal input to the differential amplifier, an insulation layer that covers the device region on the main surface, and a shield electrode that is incorporated in the insulation layer such as to conceal the device region in a plan view and that is fixed to a ground potential.

The present disclosure relates to a semiconductor device and a cell potential measuring device capable of improving measurement accuracy of a potential of a solution.A semiconductor device includes a read electrode that reads a potential of a solution, a differential amplifier, a first capacitor connected in series in a loop feeding back an output of the differential amplifier to a second input different from a first input from the read electrode, a resistance element connected in parallel with the first capacitor, and a second capacitor connected between a reference electrode indicating a reference potential and the second input. The present disclosure can be applied to, for example, a cell potential measuring device.

Methods, systems, and devices for configurable input for an amplifier are described. In some examples, a circuit may be configured to operate based on a signal having a first voltage profile or a second voltage profile. For example, the first voltage profile may be associated with a range of voltages that are based on a temperature of an associated memory chip, and the second voltage profile may be associated with a voltage (or voltages) that are not associated with the temperature of the memory chip. The circuit may include one or more transistors and switches that are activated based on the voltage profile and a switch receiving a particular control signal. In some instances, the control signal may be received based on a value stored to one or more non-volatile memory elements.