Improved dither detection, measurement, and voltage bias adjustments for an electro-optical modulator are described. The electro-optical modulator generally includes RF electrodes and phase heaters interfaced with semi-conductor waveguides on the arms of Mach-Zehnder interferometers, where a processor is connected to output a bias tuning voltage to the electro-optical modulator for controlling optical modulation. A variable gain amplifier (VGA) can be configured with AC coupling connected to receive a signal from a transimpediance amplifier (TIA) that is configured to amply a photodetector signal from an optical tap that is used to measure an optical signal with a dither signal. The analog to digital converter (ADC) can be connected to receive output from the VGA. The processor can be connected to receive the signal from the ADC and to output the bias tuning voltage based on evaluation of the signal from the tap.

Amplifier devices includes a first amplifier connected to receive an input voltage. The first amplifier outputs an internal voltage. These structures also include a second amplifier having an input node connected to receive the internal voltage and an output node outputting an output voltage. A resistive feedback loop is connected to the input node and the output node of the second amplifier. A first cross-coupled bandwidth boosting stage is connected to the input node of the second amplifier and a second cross-coupled bandwidth boosting stage connected to the output node of the second amplifier. The cross-coupled bandwidth boosting stages form a distributed differential positive feedback structure.

A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.

A transceiver interface circuit, comprising a driver amplifier (DA), a load line impedance modulation circuit coupled to the DA; and multiple selectable output ports coupled to the load line impedance modulation circuit, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of output ports coupled to the load line impedance modulation circuit.

The present disclosure provides a battery detection device. The detection circuit is disposed on the battery and produces an impedance value variation quantity according to a deformation of the battery. The detection circuit includes four connection nodes. The first connection node and the third connection node are connected with the battery. A voltage variation quantity is produced between the second connection node and the fourth connection node according to the impedance value variation quantity. The protection circuit is connected with the second connection node and the fourth connection node. The protection circuit is in an ON state when the voltage variation quantity is greater than or equal to a cut-off voltage. The protection circuit is in an OFF state when the voltage variation quantity is less than the cut-off voltage, so that an operation state of the battery is changed accordingly.

A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals. The latches receive two delayed input signals provided by the delay circuits based upon the feedback signals.

An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.

According to one embodiment, a semiconductor device includes the following configuration. A detection circuit detects a state of a clock signal. An amplification circuit changes a gain based on the state of the clock signal detected by the detection circuit. An amplification circuit amplifies a first voltage with the gain and outputs a second voltage obtained as a result of amplification. A conversion circuit converts the second voltage output from the amplification circuit to first data. An isolation circuit includes a driver and a receiver electrically isolated from the driver. The driver transmits a signal corresponding to the first data to the receiver. The receiver outputs second data corresponding to the signal transmitted from the driver. The output circuit outputs the second data output from the isolation circuit.

The present invention discloses a signal output circuit applying bandwidth broadening mechanism for an image signal transmission apparatus that includes a first driving circuit and a second driving circuit. The first driving circuit includes a continuous time linear equalizer (CTLE) and is configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a first output signal, in which a zero point and two poles of a frequency response of the first driving circuit are determined by circuit parameters thereof. The second driving circuit is configured to receive and amplify the first output signal to generate a second output signal for an image receiving apparatus.