A driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is coupled to the first operational amplifier circuit and the second operational amplifier circuit, and configured to switch at least one power supply for both the first operational amplifier circuit and the second operational amplifier circuit.

A driver circuit including a first op-amp, a second op-amp, and a power switching circuit is provided. The first op-amp includes a first input stage circuit for generating a first amplified signal and a first output stage circuit. The second op-amp includes a second input stage circuit for generating a second amplified signal and a second output stage circuit. The power switching circuit includes a first output terminal for outputting one of the first amplified signal and the second amplified signal and a second output terminal for outputting the other of the first amplified signal and the second amplified signal. The power switching circuit is configured to switch a first power supply for both the first input stage circuit and the second input stage circuit between a first supply voltage and a second supply voltage in response to the control signal.

A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

Differential sampling circuits may be adversely affected by changes in common mode voltage. Changes in the common mode voltage may alter the on resistance of transistor switches which it turn may mean that small signal changes are not correctly observed against a bigger common mode signal. The present disclosure relates to a way of improving the ability to resolve small differential signal changes by varying the supply or drive voltage to a component to compensate for common mode voltage changes.

A driver circuit including a first op-amp, a second op-amp, and a power switching circuit is provided. The first op-amp includes a first input stage circuit for generating a first amplified signal and a first output stage circuit. The second op-amp includes a second input stage circuit for generating a second amplified signal and a second output stage circuit. The power switching circuit includes a first output terminal for outputting one of the first amplified signal and the second amplified signal and a second output terminal for outputting the other of the first amplified signal and the second amplified signal. The power switching circuit is configured to switch a first power supply for both the first input stage circuit and the second input stage circuit between a first supply voltage and a second supply voltage in response to the control signal.

A transconductor circuitry (10) with adaptive biasing comprises a first input terminal (E10a) to apply a first input signal (inp), and a second input terminal (E10b) to apply a second input signal (inn). A control circuit (200) is configured to control a first controllable current source (110) in a first current path (101) and a second controllable current source (120) in a second current path (102) in response to at least one of a first potential of a first node (N1) of the first current path (101) and a second potential of a second node (N2) of the second current path (102). The first node (N1) is located between a first transistor (150) and the first controllable current source (110), and the second node (N2) is located between a second transistor (160) and the second controllable current source (120).

A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

The disclosure relates to a system and method for controlling a common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control. The differential signal processing circuit includes two load devices, two input transistors, and two current-source transistors coupled in series between voltage rails, respectively. The replica circuit includes replica load device, replica input transistor, and replica current-source transistor coupled in series between the voltage rails. The common mode voltage of the input differential signal is applied to the replica input transistor to generate a replica output common mode voltage. A feedback circuit generates a bias voltage for the replica current-source transistor and the current-source transistors of the differential circuit to set and control the replica output common mode voltage and the output common mode voltage of the differential signal processing circuit to a target common mode voltage.