Patent classifications
H03F3/45632
Capacitance decreasing scheme for operational amplifier
An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.
Charge-steering amplifier circuit and control method thereof
A charge-steering amplifier circuit and a control method thereof are provided. The charge-steering amplifier circuit is used for amplifying a differential input signal and includes a sample-and-hold circuit, a charge-steering amplifier, a reference voltage generation circuit, and a switch circuit. The sample-and-hold circuit is configured to sample the differential input signal to generate first and second sampled signals. The charge-steering amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first and second input terminals receive the first and second sampled signals, respectively. The reference voltage generation circuit is configured to generate a reference voltage according to the differential input signal. The switch circuit is configured to couple the reference voltage to the first output terminal and the second output terminal.
DYNAMIC CURRENT LIMIT FOR OPERATIONAL AMPLIFIER
An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.
Low-noise, high-accuracy single-ended input stage for continuous-time sigma delta (CTSD) analog-to-digital converter (ADC)
Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.
Differential operational transconductance amplifier for chopper-stabilized amplification
A differential operational transconductance amplifier, or DOTA, intended to be used in zero-drift precision operational amplifiers as chopper amplifier stage is disclosed. The DOTA is configured to function with a low-voltage power supply and to have good performance based on circuitry configured to provide a constant gain over a range of common-mode voltages, or VCM. The DOTA further includes bias circuitry configured to respond to the common mode voltage in order to prevent large currents, which can result from the constant gain circuitry, from negatively affecting performance. The DOTA further includes current sources that are configured to prevent temperature variations from negatively affecting performance. The DOTA further includes VCM-driven bias voltages used to optimize the operating point of the differential output stage. The DOTA uses input and input replica transistors having medium threshold voltage, which results in capability to operate at low supply voltages.
HIGH-EFFICIENCY AMPLIFIER ARCHITECTURE WITH DE-GAIN STAGE
The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.
Differential amplifier
The present document relates to differential amplifiers. A differential amplifier may comprise a current source, a first transistor, a second transistor, and a compensation circuit. A reference voltage may be applied to a first terminal of the first transistor, and a second terminal of the first transistor may be coupled to an output of the current source. A feedback voltage may be applied to a first terminal of the second transistor, and a second terminal of the second transistor may be coupled to the output of the current source. The compensation circuit may comprise a capacitive element coupled to the first terminal of the first transistor, and the compensation circuit may be configured to reduce a change of the reference voltage at the first terminal of the first transistor.
COMMON-MODE COMPENSATION IN A MULTI-LEVEL PULSE-WIDTH MODULATION SYSTEM
A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.
CURRENT CONDITIONING APPARATUS WITH NFET CURRENT MIRROR
Examples of the disclosure include a current-conditioning apparatus comprising a current mirror circuit including an input transistor adapted to receive an input current from an injection node and including an output transistor adapted to replicate in response to the received input current an output current with a predefined current mirror ratio, and a differential amplifier adapted to provide a negative feedback loop between the injection node of the apparatus and a control terminal of the input transistor of the current mirror circuit.
COMPARATOR INTEGRATION TIME STABILIZATION TECHNIQUE UTILIZING COMMON MODE MITIGATION SCHEME
Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.