A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.

A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.

A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

A device includes a sensor signal input node and a high-pass filter stage. The high-pass filter stage includes an operational amplifier and a feedback integrator. The operational amplifier includes an input node coupled to the sensor signal input node. The feedback integrator is coupled between an output node of the operational amplifier and the input node of the operational amplifier to set a high-pass pole frequency of the high-pass filter stage.

An isolation circuit and a method for providing isolation between two dies are provided. The isolation circuit includes: an isolation module, configured to generate an isolation signal based on an input signal from a first die and to provide isolation between the first die and a second die, where the isolation signal is smaller than the input signal in amplitude, and the first die is coupled with the second die; a latch module, configured to latch the isolation signal at a certain level and output a latched signal; an amplifier module, configured to amplify the latched signal. In the isolation circuit, a modulation module and a demodulation module can be saved.

Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

This application relates to circuitry for monitoring for instability of an amplifier. The amplifier (100) has a first signal path between an amplifier input (IN.sub.N) and an amplifier output (V.sub.OUT) and a feedback path from the output to form a feedback loop with at least part of the first signal path. A comparator (212) has a first input configured to receive a first signal (IN.sub.N) derived from a first amplifier node which is part of said feedback loop and a second input configured to receive a second signal (IN.sub.P) derived from a second amplifier node which varies with the signal at the amplifier input but does not form part of said feedback loop. The comparator is configured to compare the first signal to the second signal and generate a comparison signal (COMP), wherein in the event of amplifier instability the comparison signal comprises a characteristic indicative of amplifier instability.

Methods and system are described for cancelling interference in a microphone system. A positive bias voltage is applied to a first microphone diaphragm and a negative bias voltage is applied to a second microphone diaphragm. The diaphragms are configured to exhibit substantially the same mechanical deflection in response to acoustic pressures received by the microphone system. A differential output signal is produced by combining a positively-biased output signal from the first microphone diaphragm and a negatively-biased output signal from the second microphone diaphragm. This combining cancels common-mode interferences that are exhibited in both the positively-biased output signal and the negatively-biased output signal.

A Second-Generation Current Conveyor (CCII) has a three-port network with ports designated as X, Y, and Z, wherein the CCII includes a tunable feedback network. The tunable feedback network may be provided between at least two of the ports, e.g., ports Z and Y. The tunable feedback network may comprise a tunable RC (Resister-Capacitor) network which may be provided by solid-state components such as a MOS (Metal-Oxide Semiconductor) device or a MOS resistor (for the resistive element) and a varactor (for the capacitive element).

A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.