A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

The present disclosure relates an interface unit having an input for receiving an input voltage from an electrochemical measuring probe; a first transistor; a first operational amplifier; a second transistor; and a second operational amplifier. The first operational amplifier is arranged to provide a variable tension to a first source terminal of the first transistor, in accordance with a comparison between a reference voltage and a second resistor voltage, in order to control an operating point of the first transistor.

An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

A differential MEMS-readout circuit comprises a first input bonding pad, including a first contact pin and a second contact pin. The differential MEMS-readout circuit comprises a second input bonding pad, including a first contact pin and a second contact pin; and a differential-readout amplifier section comprising a first input connected to the first contact pin of the first input bonding pad and a second input connected to the first contact pin of the second bonding pad, wherein the differential-readout amplifier section comprises a first and a second transistor circuit and each of the second contact pins of the first and second input bonding pads is coupled to one of the first and the second transistor circuits or is coupled to one of the first and the second transistor circuits and/or to ground.

Methods and devices for reducing DC current consumption of a multi-stage LNA amplifier. According to one aspect, first and second amplification stages are stacked to provide a common conduction path of a DC current. The first stage includes a common-source amplifier, the second stage includes a common-drain amplifier. Coupling between the two stages is provided by series connection of load inductors of the respective stages and a capacitor coupled at a common node between the inductors. According to another aspect, a current splitter circuit is used to split a current to the first stage according to two separate conduction paths, one common path to the two stages, and another separate from the second stage. According to yet another aspect, the current splitter circuit includes a feedback loop that controls the splitting of the current so to maintain a constant current through the common path.

An amplifier circuit having an adjustable gain is provided. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal receives an input signal, which is in turn received by an input terminal of the amplifier. An output terminal of the amplifier outputs the input signal that is amplified. The attenuation circuit is coupled between the output terminal of the amplifier and the output terminal to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal, or between the input terminal and the output terminal to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.

A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A current amplifying circuit includes a first FET transistor, a light receiving unit and a functional unit. The light receiving unit is connected with a first gate terminal of the first FET transistor through an enabling line. The functional unit is connected with a second conduction terminal of the first FET transistor. When the light receiving unit absorbs a light beam, a forward photoelectric current or a reverse photoelectric current is generated. The forward photoelectric current or the reverse photoelectric current flows to the first gate terminal through the enabling line. Consequently, an enabling voltage at the first gate terminal is increased and the first FET transistor is turned on. When the first FET transistor is turned on, an enabling current flows through the first FET transistor to enable the functional unit.

An envelope tracking (ET) radio frequency (RF) front-end circuit is provided. The ET RF front-end circuit includes an ET integrated circuit(s) (ETIC(s)), a local transceiver circuit, a target voltage circuit(s), and a number of power amplifiers. The local transceiver circuit receives an input signal(s) from a coupled baseband transceiver and generates a number of RF signals. The target voltage circuit(s) generates a time-variant ET target voltage(s) based on the input signal(s). The ETIC(s) generates multiple ET voltages based on the time-variant ET target voltage(s). The power amplifiers amplify the RF signals based on the ET voltages. Given that the time-variant ET target voltage(s) is generated inside the self-contained ET RF front-end circuit, it is possible to reduce distortion in the time-variant ET target voltage(s), thus helping to improve operating efficiency of the power amplifiers, especially when the RF signals are modulated with a higher modulation bandwidth (e.g., ≥200 MHz).