An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D.sub.1) connected in parallel with the capacitive element (C), a first switching element (S.sub.1) provided in series between the first node (A) and a voltage source point, a second switching element (S.sub.2) provided between the first node (A) and a second node (Node B), a second element (D.sub.2) connected between the second switching element (S.sub.2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S.sub.1) is closed and the second switching element (S.sub.2) to charge a nodal voltage v.sub.D(t) at the first node (A). In discharge stage, the first switching element (S.sub.1) is open and the second switching element (S.sub.2) is open to enable discharging of the capacitive element (C) through the first element (D.sub.1). In a transfer stage, the second switching element (S.sub.2) is closed to connect the first node (A) and the second node (B), after which the second switching element (S.sub.2) is opened and the second element (D.sub.2) is biased to present the high-impedance load.

A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.

Provided is a compact digital attenuator. The compact digital attenuator includes a first attenuation cell to an nth attenuation cell, which include a plurality of attenuation cells connected to each other in parallel through a transmission line, wherein each of the plurality of attenuation cells may include a plurality of switch elements connected to each other in parallel, wherein the plurality of switch elements may be connected to the transmission line through one contact point.

An attenuating device for a bus of a controller area network bus system based on differential voltage signals. The bus has first and second bus lines, having an attenuating circuit that provides a variable electrical resistance value between the first and second bus lines and that is operable in at least three circuit states. In a first circuit state, the first and second bus lines are connected via an attenuating resistor having a first resistance value. In a second circuit state, the first and second bus lines are connected via an attenuating resistor having a second resistance value. In a third circuit state, the first and second bus lines are connected via an attenuating resistor having a third resistance value. The first resistance value is lower than the second resistance value. The second resistance value is lower than the third resistance value.

According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal to two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amounts of attenuation values. In the first conductive element, a first amount of attenuation is set. The high frequency integrated circuit outputs a plurality of output signals having different gain values from the first high frequency output terminal and the second high frequency output terminal, respectively.

A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

Differential attenuation circuitry, including: first and second input nodes; first and second output nodes; and an impedance network connected between the first and second input nodes and the first and second output nodes to provide a differential output voltage signal between the first and second output nodes which is attenuated compared to a differential input voltage signal applied between the first and second input nodes, wherein the impedance network includes: a common-mode node; a first impedance network connected between the first input node, the common-mode node and the first output node; and a second impedance network connected between the second input node, the common-mode node and the second output node, and wherein the differential attenuation circuitry further includes: an input-to-input path comprising one or more impedances and one or more switches connected between the first and second input nodes to provide a current path independent of the common-mode node.

Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising the steps of providing an attenuator implemented in π-topology and consisting of a serial path between the input and the output of the attenuator, including a first serial resistor Rs.sub.1 connected to the input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to the output; a first transistor T.sub.1 bridging between the input and the output, for controlling the impedance of the serial path by a first control input provided to the first transistor T.sub.1; a first parallel path between the input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a second parallel path between the output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a second control input commonly provided to first parallel transistor T.sub.2a and to the second parallel transistor T.sub.2b, for controlling the impedance of the first and second parallel paths; unifying the serial resistors to a common serial resistor Rs and splitting the serial inductor Ls to two serial inductors Ls.sub.1 and Ls.sub.2, such that one serial inductor is connected between the input and a first contract of the common serial resistor Rs and the other serial inductor is connected between the output and the other contact of the common serial resistor Rs; splitting the parallel resistor Rp.sub.1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to the first smaller resistor via the first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; splitting the parallel resistor Rp.sub.2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to the third smaller resistor via the second parallel transistor T.sub.2b and to ground via a fourth parallel transistor T.sub.3b; connecting a first feedback capacitor Cfb.sub.1 between the common point connecting between the ungrounded port of the second parallel transistor T.sub.3a and the first contract of the common serial resistor Rs and connecting a second feedback capacitor Cfb.sub.2 between the common point connecting between the ungrounded port of the fourth parallel transistor T.sub.3b and the second contract of the common serial resistor Rs; upon controlling the first and second parallel transistors T.sub.2a and T.sub.2b by the second control input, simultaneously controlling also the third and the fourth parallel tran