An embedded GPU-based wideband parallel channelized receiving method includes: constructing an OpenCL platform; decimating a wideband signal read in the OpenCL platform at an interval indicated by the number of channels; assigning data in each row to one of multiple work groups for processing; filtering data on each of channels based on a coefficient of a polyphase filter on a branch; multiplying the filtered data by a factor; and performing an FFT on the formed two-dimensional matrix by columns to obtain data outputted from each of the channels.

An embedded GPU-based wideband parallel channelized receiving method includes: constructing an OpenCL platform; decimating a wideband signal read in the OpenCL platform at an interval indicated by the number of channels; assigning data in each row to one of multiple work groups for processing; filtering data on each of channels based on a coefficient of a polyphase filter on a branch; multiplying the filtered data by a factor; and performing an FFT on the formed two-dimensional matrix by columns to obtain data outputted from each of the channels.

A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.

A subband channelizer for randomly spaced frequency groups includes: a first-stage channelizer configured to channelize a wideband input into a plurality of intermediate subbands, at least two of the plurality of intermediate subbands being partially overlapped; and a plurality of second-stage channelizers each configured to generate one or more final subbands from one of the plurality of intermediate subbands, wherein the intermediate subbands have wider bandwidth than the final subbands.

Embodiments of the present invention provide a digital signal processing apparatus, including an interpolator, an interpolating convolver, or the like, for providing a plurality of output samples or output values in parallel, such as P output samples provided by P Farrow cores, based on a set of input samples or input values, such as 2P+M−2 samples. The digital signal processing apparatus includes a sample distribution logic or structure configured to provide a plurality of subsets of the set of input samples to a plurality of processing cores, such as interpolation cores (e.g., Farrow cores) that perform processing operations associated with different time shifts, for example with respect to a reference time (e.g., a time associated with the input samples). The sample distribution logic includes a hierarchical tree structure having a plurality of hierarchical levels of splitting nodes.

Embodiments of the present invention provide a digital signal processing apparatus including a combiner logic and a plurality of processing cores. Input samples of the digital signal processing apparatus are provided to the plurality of processing cores. Sets of output samples of the processing cores are provided to the combiner logic as input samples, and the sets of samples are provided to the combiner nodes c of the highest hierarchical level (h=0). A digital signal processing apparatus or a parallel decimating digital convolver may be used as a building block of a signal processor application-specific integrated circuit (ASIC) and/or part of other instruments for generating output samples. Furthermore, applications of the digital signal processing apparatus described herein can be addressed on a parallel DSP, in a response time of real-time or near to real-time, for flexible (or almost arbitrary high) sample rates.

Polyphase filters (PPFs) can be used to generate quadrature or other phase-shifted representations of an input signal provided to the PPF. In one approach, a “passive” polyphase filter can include a combination of resistive and capacitive elements. Such a topology can be referred to as an RC-PPF topology. Another passive circuit topology can be used to provide a PPF, by replacing the resistive elements with inductive elements, and by replacing the capacitive elements with resistive elements. A filter circuit can include cascaded RC-PPF and LR-PPF sections, such as in an alternating manner (e.g., an “RC-LR” topology). In this approach, a total insertion loss of cascaded LR-PPF and RC-PPF sections can be reduced as compared to using LR-PPF or RC-PPF sections, alone.

An all-digital transmitter (ADT) is provided. The ADS includes a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band, a polyphase finite impulse response filter configured to receive and convert the baseband input signal into different phases, a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain, a set of multi-core 2-dimensional network-resonant digital plane wave beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle, a multi-core delta-sigma modulator configured to encode the upconverted input signal into pulsating signals, and a serializer configured to serialize the encoded pulsating signals into a RF bitstream.

A transmitter module for a broadband data transmission system for radio communications, comprising at least one polyphase FFT filter bank is described. The at least one polyphase FFT filter bank is established as a synthesis polyphase FFT filter bank, wherein the at least one polyphase FFT filter bank comprises several filter units, wherein the transmitter module is configured to receive an input signal comprising a symbol sequence, and wherein the transmitter module is configured to transmit a signal based on the received input signal. Moreover, a receiver module for a broadband data transmission system and a data transmission system are described.

An all-digital transmitter (ADT) is provided. The ADS includes a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band, a polyphase finite impulse response filter configured to receive and convert the baseband input signal into different phases, a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain, a set of multi-core 2-dimensional network-resonant digital plane wave beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle, a multi-core delta-sigma modulator configured to encode the upconverted input signal into pulsating signals, and a serializer configured to serialize the encoded pulsating signals into a RF bitstream.