A temperature sensor using a poly-phase filter may include: a poly-phase filter suitable for receiving a divided clock, and having passive elements coupled to have one or more negative poles and one or more positive zeros; a comparator suitable for generating a reference clock by comparing potentials of first and second filter voltages outputted from the poly-phase filter; a phase frequency detector suitable for outputting an up or down signal by comparing the phase of the reference clock to the phase of a comparison clock; a current supply unit suitable for supplying and integrating a charge current under control of the up or the down signal; an oscillator suitable for outputting an oscillation signal; a divider suitable for generating the divided clock and the comparison clock; and a buffer suitable for inverting and non-inverting the divided clock and outputting the inverted and non-inverted divided clocks.

A transmitter module for a broadband data transmission system for radio communications, comprising at least one polyphase FFT filter bank is described. The at least one polyphase FFT filter bank is established as a synthesis polyphase FFT filter bank, wherein the at least one polyphase FFT filter bank comprises several filter units, wherein the transmitter module is configured to receive an input signal comprising a symbol sequence, and wherein the transmitter module is configured to transmit a signal based on the received input signal. Moreover, a receiver module for a broadband data transmission system and a data transmission system are described.

A temperature sensor using a poly-phase filter may include: a poly-phase filter suitable for receiving a divided clock, and having passive elements coupled to have one or more negative poles and one or more positive zeros; a comparator suitable for generating a reference clock by comparing potentials of first and second filter voltages outputted from the poly-phase filter; a phase frequency detector suitable for outputting an up or down signal by comparing the phase of the reference clock to the phase of a comparison clock; a current supply unit suitable for supplying and integrating a charge current under control of the up or the down signal; an oscillator suitable for outputting an oscillation signal; a divider suitable for generating the divided clock and the comparison clock; and a buffer suitable for inverting and non-inverting the divided clock and outputting the inverted and non-inverted divided clocks.

A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

The device (8) for decimating samples of a continuous signal by a float number. The device includes interpolating means (11) configured to determine intermediate samples. A determining means (12) is configured to determine intermediate set of samples comprising the samples and the intermediate samples. A filtering means (13) is configured to filter the intermediate set of samples to determine one final value from an odd number of consecutive samples of the intermediate set of samples and to remove frequencies below a first cut-off frequency (F3) equal to the predetermined sampling frequency divided by two within a predetermined tuning value.

Systems (400) and methods for reducing a number of cyclostationary features in a transmitted signal. The methods comprise: obtaining by a transmitter a discrete-time IF signal comprising a sequence of samples all having a same sample duration; performing operations by a sub-sample dithering processing device of the transmitter to modify a sample timing of the discrete-time IF signal by decreasing or increasing a duration of at least one first sample of the sequence using a digital signal processing technique in a digital domain; converting the discrete-time IF signal to an RF signal; and transmitting the RF signal having a reduced number of cyclo stationary features.

A spot noise generator includes a mask component, a polyphase synthesizer, a first signal channel and second signal channel. The mask component has a narrowband noise input, a desired frequency channels word input, a first channel output and a second channel output. The narrowband noise input signal is a digital narrowband noise signal sampled approximately at the Nyquist rate. The desired frequency channels word selects one of the group consisting of the first channel output, the second channel output and a combination of the first channel output and the second channel output. The polyphase synthesizer synthesizes the first channel output signal, synthesizes the second channel output signal and outputs a desired noise signal based on the synthesized first channel output signal and the synthesized second channel output signal.

A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

Circuit and method for modulating filter coefficients of a frequency channelizer having a filter bank include: receiving a wide spectrum input signal; modulating the filter coefficients of the filter bank to sweep a center frequency of each channel of the frequency channelizer, using a modulation scheme; and inputting frequency offset compensation caused by the modulation, and output signals of the frequency channelizer to an application processing circuit to convert the output signals to their original center frequencies.