A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.

A digital filter structure and related method of digital filtering are presented. The digital filter structure is arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate. The digital filter structure has a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of the digital filter structure, a filter operation is performed on a different stream of data. The disclosure can be applied in many different contexts. One particular implementation example is that of an adaptive noise cancellation (ANC) system using sigma-delta infinite impulse response filters. In this context the present disclosure minimizes latency and hardware implementation area by requiring only one filtering circuit for multiple channels of data to be filtered.

A filter circuit includes a first stage comprising a first infinite impulse response (IIR) filter; a third stage comprising a third IIR filter; and a second stage interposed between the first stage and the third stage, the second stage comprising a second IIR filter, where an output terminal of the first IIR filter is coupled to an input terminal of the second IIR filter, and an output terminal of the second IIR filter is coupled to an input terminal of the third IIR filter, where the second stage of the filter circuit is configured to operate in an acquisition mode when a transient is detected in an input signal to the first IIR filter, where during the acquisition mode, the second stage of the filter circuit is bypassed.

A filter circuit includes a first stage comprising a first infinite impulse response (IIR) filter; a third stage comprising a third IIR filter; and a second stage interposed between the first stage and the third stage, the second stage comprising a second IIR filter, where an output terminal of the first IIR filter is coupled to an input terminal of the second IIR filter, and an output terminal of the second IIR filter is coupled to an input terminal of the third IIR filter, where the second stage of the filter circuit is configured to operate in an acquisition mode when a transient is detected in an input signal to the first IIR filter, where during the acquisition mode, the second stage of the filter circuit is bypassed.

A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.

A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.

A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.

A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.