An audio processing system and method of operating the system are provided. The system includes a memory storing a plurality of frequency domain sound recording samples represented and stored in a frequency domain and being previously converted from a plurality of sound recording samples represented in a time domain. The system also includes at least one processing unit coupled to the memory and is configured to read the plurality of frequency domain sound recording samples from the memory. The at least one processing unit is also configured to process the plurality of frequency domain sound recording samples.

A method for offset calibration of a rotation rate sensor signal of a rotation rate sensor. In a first step, an ascertainment is made that the rotation rate sensor is in an idle state. In a second step, after the first step, a filter parameter is determined as a function of the measured rotation rate sensor values, measured in the idle state, of the rotation rate sensor. In a third step, after the second step, a filtered measured rotation rate sensor value is determined with the aid of the filter parameter. An offset is determined with the aid of the filtered measured rotation rate sensor value.

A method for offset calibration of a rotation rate sensor signal of a rotation rate sensor. In a first step, an ascertainment is made that the rotation rate sensor is in an idle state. In a second step, after the first step, a filter parameter is determined as a function of the measured rotation rate sensor values, measured in the idle state, of the rotation rate sensor. In a third step, after the second step, a filtered measured rotation rate sensor value is determined with the aid of the filter parameter. An offset is determined with the aid of the filtered measured rotation rate sensor value.

An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

The present invention addresses the problem of reducing a circuit scale without causing a reduction in processing efficiency. This multi-stage filter processing method measures, at each stage, either the number of input data or the number of intermediate data that is generated by filter calculation processing during the stages before the final stage is reached. Coefficient data regulating for each stage the number of data sufficient to perform the filter calculation processing is held. Input data or the intermediate data that is generated in a current stage is held in a memory until the number of data reaches the number of data sufficient to perform the filter calculation processing in the current stage, on the basis of the coefficient data. When the number of data has reached, the filter calculation processing for the current stage is performed on the input data or the intermediate data that was held.

Systems, methods, and other embodiments associated with converting an input signal into an output signal with a different sampling rate. In one embodiment, an apparatus includes a feedforward circuit configured to receive the input signal comprised of discrete data samples with the first sampling rate and to generate a first intermediate value based, at least in part, on a feedforward coefficient and the input signal. The apparatus includes a feedback circuit configured to generate a second intermediate value that is based, at least in part, on a feedback coefficient and a predetermined number of previous samples of the output signal. The apparatus includes a signal combiner configured to combine the first intermediate value and the second intermediate value together to interpolate a data sample of the output signal at the second sampling rate. The output signal is a converted form of the input signal at the second sampling rate.