Patent classifications
H03H2017/0232
CONFIGURABLE MULTIPLIER-FREE MULTIRATE FILTER
A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.
Configurable multiplier-free multirate filter
A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.
Reducing crest factors
The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.
REDUCING CREST FACTORS
The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.