A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.

The present disclosure relates to a digital filter arrangement (DFA) for compensating group velocity dispersion (GVD) in an optical transmission system (OTS) wherein the DFA is configured to receive a sequence of samples of a digital input signal in the time domain in the form of consecutive blocks of size L. The DFA is configured to generate M discrete Fourier transforms of a current overlap block of a size N greater than the size L and of M−1 delayed versions of the current overlap block. The DFA is configured to filter the entries of the generated M discrete Fourier transforms to generate an output discrete Fourier transform with N entries, wherein the compensation filter is implemented by a delay network and a linear combination algorithm.

A frequency converter comprising a frequency transposition block for samples (11.sub.Q.sub._.sub.1, 11.sub.Q.sub._.sub.2), a filtering block (12.sub.Q.sub._.sub.1, 12.sub.Q.sub._.sub.2), the filtered samples y(n) verifying y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2)+ . . . +c(p−1).Math.x(n−p+1)+c(p).Math.x(n−p)+c(p−1).Math.x(n−p−1)+ . . . + . . . +c(1).Math.x(n−2.Math.p+1)+c(0).Math.x(n−2.Math.p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0).Math.x(n), c(1).Math.x(n−1), c(2).Math.x(n−2), . . . , c(p).Math.x(n−p) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p−1).Math.x(n−p−1), . . . , c(1).Math.x(n−2.Math.p+1), c(0).Math.x(n−2.Math.p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(n−m); and determining y(n) by summation of the first and second terms.

Systems and methods for direct signal down-conversion and decimation in a digital receiver. The digital receiver produces a decimated passband version of the signal without the problems associated with use of digital mixers. The digital receiver includes a passband-to-passband decimator/down-converter that implements an algorithm which takes the signal band (frequency and bandwidth or lower and upper frequencies) where a signal is present and produces a decimation rate and phase for use by a low-pass mixer-free down-conversion. The digital receiver technology may be efficiently implemented on a digital signal processor or field-programmable gate array.

The invention relates to a method for simplifying a sampled signal digital filter, the method including at least one step for: in order to obtain a first intermediate filter, gathering channels including discrete nonstationary operations relating to the same signal, the first channels including the nonstationary operations relating to a first signal and the second channels including the nonstationary operations relating to a second signal, in order to obtain a second intermediate filter, on each of the first channels and second channels, commutative stationary operations with the nonstationary operations, in order to eliminate the redundant nonstationary operations, and building the filter corresponding to the last obtained intermediate filter.

The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method including at least one step for: obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2.sup.p points on a signal coming from the input signal, the integer p being greater than or equal to 1, applying an inverse discrete Fourier transform to M/2.sup.p points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

Systems and methods for direct signal down-conversion and decimation in a digital receiver. The digital receiver produces a decimated passband version of the signal without the problems associated with use of digital mixers. The digital receiver includes a passband-to-passband decimator/down-converter that implements an algorithm which takes the signal band (frequency and bandwidth or lower and upper frequencies) where a signal is present and produces a decimation rate and phase for use by a low-pass mixer-free down-conversion. The digital receiver technology may be efficiently implemented on a digital signal processor or field-programmable gate array.

Embodiments of the present invention provide a digital signal processing apparatus, including an interpolator, an interpolating convolver, or the like, for providing a plurality of output samples or output values in parallel, such as P output samples provided by P Farrow cores, based on a set of input samples or input values, such as 2P+M−2 samples. The digital signal processing apparatus includes a sample distribution logic or structure configured to provide a plurality of subsets of the set of input samples to a plurality of processing cores, such as interpolation cores (e.g., Farrow cores) that perform processing operations associated with different time shifts, for example with respect to a reference time (e.g., a time associated with the input samples). The sample distribution logic includes a hierarchical tree structure having a plurality of hierarchical levels of splitting nodes.

Embodiments of the present invention provide a digital signal processing apparatus including a combiner logic and a plurality of processing cores. Input samples of the digital signal processing apparatus are provided to the plurality of processing cores. Sets of output samples of the processing cores are provided to the combiner logic as input samples, and the sets of samples are provided to the combiner nodes c of the highest hierarchical level (h=0). A digital signal processing apparatus or a parallel decimating digital convolver may be used as a building block of a signal processor application-specific integrated circuit (ASIC) and/or part of other instruments for generating output samples. Furthermore, applications of the digital signal processing apparatus described herein can be addressed on a parallel DSP, in a response time of real-time or near to real-time, for flexible (or almost arbitrary high) sample rates.

Disclosed are an audio rate conversion system and an electronic apparatus. The audio rate conversion system includes an integrator-comb filter, a multi-rate filter and a first half-band filter, an input of the integrator-comb filter being accessed with digital audio data, an output of the integrator-comb filter being sequentially connected to the multi-rate filter and the first half-band filter; where, the integrator-comb filter is configured to reduce a rate of the digital audio data according to a preset decimation rate; the multi-rate filter is configured to convert a rate of digital audio data output by the integrator-comb filter into a rate of digital audio data corresponding to an accessed control signal according to the control signal; and the first half-band filter is configured to reduce a rate of digital audio data output by the multi-rate filter.