A pre-charge control circuit includes a control unit, a conversion unit, and a pre-charge switch. The control unit provides a control signal according to a PWM signal, and the conversion unit provides a control voltage according to the control signal. The pre-charge switch adjusts a magnitude of the current flowing through the input path of the electronic circuit according to the control voltage.

A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

A switching regulator includes a first switch circuit, a second switch circuit, and a protection circuit. The first switch circuit has a first connection node coupled to a first reference voltage, and a second connection node coupled to one end of an inductor. The second switch circuit has a first connection node coupled to a second reference voltage, and a second connection node coupled to the one end of the inductor. The protection circuit senses a voltage level at the first connection node of the first switch circuit, and selectively enables an auxiliary current path in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection fashion.

Embodiments of an SMPS controller and a method for operating a switched-mode power supply (SMPS) controller are described. In an embodiment, an SMPS controller includes a gate driver circuit configured to generate a drive signal for a switch of an SMPS and a current sense electrical terminal configured to receive sensed current corresponding to the switch and to conduct driver discharge current from the gate driver circuit.

It is provided a driving system, a driving method, a computer system and a computer readable medium. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjusting circuit configured to automatically detect a present amplitude of the on-chip voltage output by the input circuit and to output a bias voltage corresponding to the present amplitude of the on-chip voltage to a gate of the driven thin film transistor, wherein a source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. The protection of the transistor gate and the adjusting of a receiver threshold voltage for different I/O (input/output) voltages and levels can be completed through automatic detection of the on-chip voltage and automatic adjusting.

An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.

A semiconductor device according to an embodiment includes a normally-off transistor having a first source, a first drain, and a first gate; a normally-on transistor having a second source electrically connected to the first drain, a second drain, and a second gate, a capacitor having a first end and a second end, the second end being electrically connected to the second gate, a first diode having a first anode electrically connected between the second end and the second gate and having a first cathode electrically connected to the second source, a first resistor provided between the first end and the first gate, and a second diode having a second anode electrically connected to the first end and having a second cathode electrically connected to the first gate, the second diode being provided in parallel with the first resistor.

A level conversion circuit includes a first pin, a second pin, a target pin, a core module and a switch. A first terminal of the switch is connected to the first pin, a second terminal of the switch is connected to the second pin, and the core module is connected to the target pin, the second pin and a control terminal of the switch respectively. The core module is configured to: when a voltage connected to the target pin is at a first reference high level, control the switch to turn on to transmit a signal with a specified voltage amplitude, and pull the first pin to the first reference high level and the second pin to a second reference high level based on the first reference high level; where the first reference high level is higher than the second reference high level.

A current path to a gate is cut off by a normally-off first switch element until start-up of a gate drive voltage generator is sensed. Furthermore, a semiconductor switching element is maintained in an off state as a normally-on second switch element short-circuits the gate to a source. As start-up of the gate drive voltage generator is sensed, the second switch element is turned off and the first switch element is turned on. As the gate is thus driven by an output from a signal amplifier in accordance with a control signal, the semiconductor switching element is turned on and off in accordance with the control signal.

An apparatus includes a transistor coupled to a load through an output terminal of a load switch IC, a gate drive circuit connected to a gate of the transistor, wherein the gate drive circuit is configured such that in a short circuit event, a voltage on the gate of the transistor is gradually reduced, and wherein as a result of reducing the voltage on the gate of the transistor gradually, a negative voltage occurring at the output terminal of the load switch IC is minimized.