A semiconductor device includes a MOSFET including a drift layer, a channel layer, a trench gate structure, a source layer, a drain layer, a source electrode, and a drain electrode. The trench gate structure includes a trench penetrating the channel layer and protruding into the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film. A portion of the trench protruding into the drift layer is entirely covered with a well layer, and the well layer is connected to the channel layer.

A solid state relay and a method for controlling a signal path between an AC-signal output and a load in a power amplifier assembly are disclosed. The relay comprises a first and a second MOSFET having a common gate junction, a common source junction and wherein and wherein a drain terminal of a first MOSFET and a drain terminal of a second MOSFET form relay terminals. The solid state relay further comprises a control circuit comprising a positive side comprising a first controlled current generator configured to provide a first control current to the gate junction, and a negative side comprising a current mirror circuit configured to sink a second current from the source junction. Hereby, a generic solid state speaker relay has been disclosed. The relay performs up to the most stringent demands regarding pop/click on high quality products. It can be used to ground wire break, hot wire break and BTL (Bridge Tied Load) break. The design is rather tolerable to different MOSFETs and very competitive in quality and price.

A method and apparatus are provided for controlling a drive terminal of a power transistor by applying a turn-off voltage to the drive terminal at a turn-off time, measuring a gate current at the drive terminal to detect a predetermined gate current slope, determining a first time increment after the turn-off time when the predetermined gate current slope is detected, determining a second time increment which is proportional to the first time increment and which expires within a Miller plateau for the power transistor, and lowering the gate current at the drive terminal to a predetermined current level upon expiration of the second time increment in order to reduce overvoltages at the power transistor.

In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.

A frequency-locked circuit for a variable frequency topology is configured to trigger a Pulse Width Modulation (PWM) controller to lock a frequency of a driving signal outputted by the PWM controller. The frequency-locked circuit includes an AC wave generating circuit and a comparator. The AC wave generating circuit receives and converts the driving signal to generate an AC wave signal. The comparator is electrically connected to the AC wave generating circuit and receives the AC wave signal. The comparator compares the AC wave signal with a reference signal to generate a comparison output signal. In response to determining that the AC wave signal is greater than the reference signal, the comparison output signal triggers the PWM controller to convert the driving signal from one voltage level to another voltage level so as to lock the frequency. The one voltage level is different from the another voltage level.

An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.

A method for controlling an electrical switch using a driver waveform, wherein the driver waveform comprises: a first time period, T.sub.1, associated with a first current, I.sub.G_high; a second time period, T.sub.2, associated with a second current, I.sub.G_low; wherein: the first current of the driver waveform, I.sub.G_high, is larger than the second current of the driver waveform, I.sub.G_low; and the first time period, T.sub.1, has a first duration and the second time period, T.sub.2, has a second duration. The method comprising: determining an optimised first duration by repeatedly modifying the first duration until an overshoot in an output waveform generated by switching the electrical switch using the driver waveform is less than a threshold; determining an optimised second duration based on the optimised first duration; and switching the electrical switch using the optimised first duration and the optimised second duration.

A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.

A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

Laser driver designs that aim to reduce or eliminate the problem of fault laser firing are disclosed. Various laser driver designs presented herein are based on providing a current dissipation path that is configured to start providing a resistance for dissipating at least a portion, but preferably substantially all, of the negative current from the laser diode. Dissipating at least a portion of the negative current may decrease the unintentional increase of the voltage at the input to the laser diode and, therefore, reduce the likelihood that fault laser firing will occur. A control logic may be used to control the timing of when the current dissipation path is activated (i.e., provides the resistance to dissipate the negative current from the laser diode) and when it is deactivated.