The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.

A source driver circuit can include: (i) a control transistor having a control terminal and first and second power terminals, where the control transistor is coupled between a power terminal of a main switching transistor and ground; (ii) a power supply capacitor coupled between the control terminal of the main switching transistor and ground, where the power supply capacitor is configured to receive a bias voltage that is substantially constant; (iii) a freewheeling diode having a cathode coupled to a control terminal of the main switching transistor, and an anode coupled to the second power terminal of the main switching transistor; and (iv) the control transistor being controllable to be periodically turned on and off to control the main switching transistor to correspondingly follow on and off states of the control transistor.

A hybrid switch apparatus includes a gate drive circuit producing a gate drive signal, a GaN high electron mobility transistor (HEMT) having a first gate, a first drain, and a first source. A silicon (Si) MOSFET has a second gate, a second drain, and a second source. The GaN HEMT and the Si MOSFET are connected in a parallel arrangement so that (i) the first drain and the second drain are electrically connected and (ii) the first source and the second source are electrically connected. The second gate is connected to the gate drive circuit output to receive the gate drive signal. A delay block has an input connected to the gate drive circuit output and an delay block output is configured to produce a delayed gate drive signal for driving the GaN HEMT.

A bridge leg circuit assembly comprising: a circuit board, a first active switch die, and a second active switch die. The circuit board having an insulating plate with a first and second side and a first and second conducting layer on the first and second sides of the insulating plate, respectively. The second conducting layer having a first and second conducting region that are insulated from each other. The first active switch die having an opposing first side, facing and coupled with the first conducting region, and an opposing second side, coupled with the second conducting region, which are embedded into the circuit board. The second active switch die having an opposing first side, coupled with the second conducting region, and an opposing second side, coupled with the first conducting layer, which are embedded into the circuit board.

A protective circuit for a semiconductor switch includes a clamp diode, an NPN bipolar transistor, a PNP bipolar transistor, a capacitor connected in parallel with the base-emitter path of the PNP bipolar transistor, and at least three resistors. The bipolar transistors are connected to a thyristor structure that is connected to the cathode of the clamp diode. A first resistor is connected in parallel with the base-emitter path of the NPN bipolar transistor. A first terminal of the second resistor is connected to the base of the PNP bipolar transistor. Either a third resistor is connected in parallel with the base-emitter path of the PNP bipolar transistor, or a first terminal of the third resistor is connected to the emitter of the PNP bipolar transistor and the second terminal of the third resistor is connected to the second terminal of the second resistor.

A multi-transistor configuration including a first transistor having a first terminal that is configured to control the flow of current between, a second terminal of the first transistor and a third terminal of the first transistor; a second transistor, that is a bipolar junction transistor comprising a base terminal, an emitter terminal, and a collector terminal, wherein the third terminal of the first transistor and the collector terminal of the second transistor are electrically connected; and a first voltage source having a first terminal at a first voltage and a second terminal at a second voltage.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.

A driving circuit includes first and second driving units connected in parallel to each other, wherein both the first and second driving units start to supply a gate current to a gate of a switching device in a turn-on operation of the switching device, when a gate voltage of the switching device increases and has reached a threshold voltage of the switching device, the first driving unit continues to supply the gate current, and the second driving unit stops supply of the gate current before the gate voltage has reached the threshold voltage.

In a method for controlling a direct current switch having first and second semiconductor switches capable of being switched off, the first and second semiconductor switches are arranged between first and second terminals to enable conduction of a current with a first polarity through the first semiconductor switch and conduction of the current with a second polarity that is opposite to the first polarity through the second semiconductor switch. One of the first and second semiconductor switches is switched off as a function of a current measurement value.