A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

A novel programmable logic device is provided. Programmable switches each include a first transistor and a second transistor. The first transistor in a first programmable switch controls conduction between a first wiring and a gate of the second transistor in the first programmable switch. The second transistor in the first programmable switch controls conduction between the first wiring and a second wiring. The first transistor in the second programmable switch controls conduction between another first wiring and a gate of the second transistor in the second programmable switch.

A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

A power switching cell, and associated multi-level converter, include an input port capable of receiving a switching control signal, an input transistor linked by the gate to the input port, and by the source to a reference voltage, a self-biasing circuit comprising a self-biasing transistor linked by the gate to the drain of the input transistor, and a resistor connected in parallel between the gate and the source of the self-biasing transistor, and in series between the drain of the input transistor and the source of the self-biasing transistor, a power transistor, linked by the gate to the source of the self-biasing transistor and by the drain to a power supply voltage, and an isolating transistor linked by the gate and by the source to the gate and to the source of the power transistor, and by the drain to the output port of the cell.

A current source logic gate with depletion mode field effect transistor (FET) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.