A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A port controller device includes a pull-up resistor, a switching circuit, an enabling circuitry, and a protection circuitry. The pull-up resistor is configured to be coupled to a port, in which the port is configured to be coupled to a channel configuration pin of an electronic device. The switching circuit is configured to selectively transmit a supply voltage to the port via the pull-up resistor according to a first control signal, and turn off a signal path between the pull-up resistor and the port according to a second control signal. The enabling circuitry is configured to generate the first control signal according to an enable signal and the supply voltage. The protection circuitry is configured to generate the second control signal in response to a voltage from the port when the supply voltage is not powered, in order to limit a current from the port.

A port controller device includes a pull-up resistor, a switching circuit, an enabling circuitry, and a protection circuitry. The pull-up resistor is configured to be coupled to a port, in which the port is configured to be coupled to a channel configuration pin of an electronic device. The switching circuit is configured to selectively transmit a supply voltage to the port via the pull-up resistor according to a first control signal, and turn off a signal path between the pull-up resistor and the port according to a second control signal. The enabling circuitry is configured to generate the first control signal according to an enable signal and the supply voltage. The protection circuitry is configured to generate the second control signal in response to a voltage from the port when the supply voltage is not powered, in order to limit a current from the port.

An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

According to one embodiment, a semiconductor device includes an output circuit; a detection circuit; and a control circuit. The output circuit includes a first transistor which includes one end of a current path connected to an output node, receives a first input signal, and outputs a first voltage, and a second transistor which includes one end of a current path connected to the output node, receives a second input signal, and outputs a second voltage. The output circuit outputs the first voltage or the second voltage. The detection circuit detects the voltage and outputs a detection result. The control circuit controls back-gate potentials of the first and the second transistors.

According to one embodiment, a semiconductor device includes an output circuit; a detection circuit; and a control circuit. The output circuit includes a first transistor which includes one end of a current path connected to an output node, receives a first input signal, and outputs a first voltage, and a second transistor which includes one end of a current path connected to the output node, receives a second input signal, and outputs a second voltage. The output circuit outputs the first voltage or the second voltage. The detection circuit detects the voltage and outputs a detection result. The control circuit controls back-gate potentials of the first and the second transistors.

A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.