Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.

A die includes one or more power delivery layers to deliver power within the die. Additionally, the die also includes one or more transistor layers to at least partially implement a programmable fabric for the die. Furthermore, the die further includes one or more signal routing layers to transmit signals for use by the programmable fabric. Moreover, the one or more transistor layers physically separate the one or more power delivery layers from the one or more signal routing layers.

A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

A control circuit including a quadrature encoder circuit, a counter circuit, and a cutoff circuit is provided. The quadrature encoder circuit generates a first edge signal and a first direction signal according to a first external signal and a second external signal. The counter circuit performs a counting operation according to the first edge signal and the first direction signal. In response to the timer signal being enabled, the cutoff circuit prevents the first edge signal and the first direction signal from entering the counter circuit and provides a second edge signal and a second direction signal to the counter circuit so that the counter circuit performs the counting operation according to the second edge signal and the second direction signal.

Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

A system includes a first cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs, a first plurality of buffering devices receiving the first plurality of clock outputs and outputting a first plurality of buffered clock signals synchronized with each other, a first plurality of connectors receiving the first plurality of buffered clock signals and outputting a plurality of blade signals to a plurality of blades. Each blade includes a plurality of programmable logic devices, an operation of which is synchronized based on the first plurality of clock inputs. Each blade includes a second cross-point switch to receive a blade signal of the plurality of blade signals. The second cross-point switch outputs a second plurality of clock outputs based on the received blade signal, and the second plurality of clock outputs are provided to the programmable logic devices.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.