A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal. The third set of flip-flops outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal. The third set of flip-flops outputs the set of rising data portions and the fourth set of flip-flop circuits outputs the set of falling data portions to generate a synchronized data stream to output to the array data bus in response to a common clock signal.

A memory sub-system including a memory device, wherein the memory device includes a circuit, operatively coupled to an array data bus of a memory array, and control logic, operatively coupled with the circuit, to perform operations including: deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.

A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

A circuit includes a flip-flop included in a multi-stage shift register and a control element. The flip-flop includes an output field-effect transistor, a first field-effect transistor configured to operate to supply one of a high potential and a low potential to the gate of the output field-effect transistor, and a second field-effect transistor configured to operate to supply the other one of the high potential and the low potential to the gate of the output field-effect transistor. The control element is configured to operate to make an electric current flow between the gate and a power supply in the opposite direction of an off-leakage current from at least either one of the first field-effect transistor and the second field-effect transistor in a period where the first field-effect transistor and the second field-effect transistor are off.

A clock data recovery circuit configured to receive an input data signal that includes an embedded clock signal includes a clock recovery circuit including a phase detector configured to detect a phase of the embedded clock signal and to generate a recovery clock signal from the input data signal based on the detected phase; and a data recovery circuit configured to generate a recovery data signal from the input data signal by using the recovery clock signal. The phase detector includes a sampling latch circuit configured to output a first sample signal and a second sample signal from the input data signal; and an edge detection circuit configured to generate a phase control signal based on the first sample signal and the second sample signal and output the phase control signal in a period in which the second sample signal is output from the sampling latch circuit.

A circuit includes a flip-flop included in a multi-stage shift register and a control element. The flip-flop includes an output field-effect transistor, a first field-effect transistor configured to operate to supply one of a high potential and a low potential to the gate of the output field-effect transistor, and a second field-effect transistor configured to operate to supply the other one of the high potential and the low potential to the gate of the output field-effect transistor. The control element is configured to operate to make an electric current flow between the gate and a power supply in the opposite direction of an off-leakage current from at least either one of the first field-effect transistor and the second field-effect transistor in a period where the first field-effect transistor and the second field-effect transistor are off.

A serializer includes: a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data; a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal.

An architecture for high-performance flip-flops having minimal clock-activated transistors is disclosed. The flip-flops operating in a first voltage domain can receive an input signal from a second voltage domain. The flip-flops include a first latch electrically coupled to a second latch. The first latch includes a first output and a second output. The second latch further includes a first and a second keeper pull-up sub-circuit which electrically couples to the first and second output of the first latch. The clock-gating functionality of the first and second keeper pull-up sub-circuits is merged with the first latch to reduce the loading on the clock signal, and thus the operation of the flip-flop is contention-free and fully-static. An embodiment of the second latch includes only one clock-activated transistor for low-power application. Another embodiment includes two clock-activated transistors for high-speed application. The high-performance flip-flops have near-zero setup time and a two-stage propagation delay.

A transceiver device includes a pulse generator, an output node, and an internal bus that couples the pulse generator and the output node. The pulse generator is configured to selectively add at least one pulse to an outlet power supply signal conveyed by the internal bus to the output node, wherein the pulse generator includes a bootstrap capacitor with a first side coupled to the internal bus and a second side selectively coupled to at least one current source. A transceiver method includes receiving an inlet power supply signal and providing an outlet power supply signal to an output node, wherein the outlet power supply signal is based on the inlet power supply signal. The transceiver method also includes selectively adding a sync or data pulse to the outlet power supply signal based on a pulse scheme and a bootstrap capacitor coupled to the output node.