Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.

A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

A level shifter may include: a discharge circuit configured to receive an input signal on the basis of a first power supply voltage, and discharge an internal node on the basis of the input signal; a charge supply circuit configured to supply charge to an output node from which an output signal is outputted, on the basis of a second power supply voltage; and a voltage adjustment circuit including a first MOS transistor coupled between the internal node and the output node, and configured to adjust the voltage of the output node on the basis of a bias voltage applied to the first MOS transistor, and stop the operation of adjusting the voltage of the output node on the basis of the bias voltage, when the levels of the first and second power supply voltages are equal to each other.

Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.

An active pull-up circuit which is operated between an upper voltage and a lower voltage and which pulls up an intermediate node to the upper voltage in reaction to an input voltage of the pull-up circuit falling from the upper voltage to an intermediate voltage is described. The pull-up circuit comprises a first transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to the input voltage. The pull-up circuit comprises a second transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to a control node. In addition, the pull-up circuit comprises control circuitry configured to pull the control node to a voltage level of the intermediate node, subject to the input voltage falling from the upper voltage to the intermediate voltage.

A circuit includes a control inverter, a first latch circuit, and a second latch circuit. The control inverter receives a control signal to generate a reverse control signal. The first latch circuit is activated by the reverse control signal to convert a first input signal ranging from the first supply voltage to the ground into a first output signal ranging from the second supply voltage to the ground. The second latch circuit is activated by the reverse control signal to convert a second input signal ranging from a first supply voltage to the ground into a second output signal ranging from the second supply voltage to the ground. The first supply voltage and the second supply voltage are different.

The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.