A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

A level shifter may include: a discharge circuit configured to receive an input signal on the basis of a first power supply voltage, and discharge an internal node on the basis of the input signal; a charge supply circuit configured to supply charge to an output node from which an output signal is outputted, on the basis of a second power supply voltage; and a voltage adjustment circuit including a first MOS transistor coupled between the internal node and the output node, and configured to adjust the voltage of the output node on the basis of a bias voltage applied to the first MOS transistor, and stop the operation of adjusting the voltage of the output node on the basis of the bias voltage, when the levels of the first and second power supply voltages are equal to each other.

A circuit includes a control inverter, a first latch circuit, and a second latch circuit. The control inverter receives a control signal to generate a reverse control signal. The first latch circuit is activated by the reverse control signal to convert a first input signal ranging from the first supply voltage to the ground into a first output signal ranging from the second supply voltage to the ground. The second latch circuit is activated by the reverse control signal to convert a second input signal ranging from a first supply voltage to the ground into a second output signal ranging from the second supply voltage to the ground. The first supply voltage and the second supply voltage are different.

The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Apparatus and methods for radio frequency (RF) switch control are provided. In certain embodiments, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a negative charge pump voltage and a first output that provides a first switch control signal, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor and controlled by a first switch enable signal.

Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111 P) is configured to output a first intermediate voltage (V.sub.SAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.

A level shifter circuit for translating input signal to output signal is disclosed. The level shifter includes an input stage and a latch stage. The latch stage comprises at least a transistor characterized in a substantially matched transconductance with the input stage for preventing a discrete realization of a voltage clamp circuit. The transistor is a semiconductor device including a source region having a source doping region and a drain region having a first doping region and a second doping region. The first doping region is doped with a first conductivity impurity. The second doping region is disposed around the first doping region so as to surround the first doping region, and is doped with a second conductivity impurity. The second doping region has a higher on-resistance than the first doping region, thereby a high resistive series path is created by the second doping region to mimic an embedded resistor.