An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

Apparatuses and methods for reducing vertical fixed pattern noise in imaging systems are disclosed herein. An example apparatus may include an analog dithering circuit coupled to randomly add an offset voltage to a first reference voltage in response to a random binary signal during an analog to digital conversion operation, and a ramp generator circuit coupled to receive the first reference voltage, and provide a second reference voltage in response, wherein the randomly added offset voltage to the first reference is also present in the second reference voltage.

Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time.

This disclosure relates to systems and/or methods for subtracting in the current domain an output current primary signal from a primary sensor from an output current reference signal from a reference sensor to produce a frequency output signal indicative of the difference between the output current primary signal and the output current reference signal.

This disclosure relates to systems and/or methods for subtracting in the current domain an output current primary signal from a primary sensor from an output current reference signal from a reference sensor to produce a frequency output signal indicative of the difference between the output current primary signal and the output current reference signal.

Apparatuses and methods for image sensors with increased analog to digital conversion range are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to a ramp voltage input of the comparator, increasing, by a ramp generator, an auto-zero voltage level of a ramp voltage provided to the ramp voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to a bitline input of the comparator.

Apparatuses and methods for image sensors with increased analog to digital conversion range are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to a ramp voltage input of the comparator, increasing, by a ramp generator, an auto-zero voltage level of a ramp voltage provided to the ramp voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to a bitline input of the comparator.

In an embodiment a direct current to direct current (DC-DC) converter includes a first switching circuit configured to switch a supply of an input voltage to an energy storage circuit configured to generate an output voltage, a driving circuit configured to drive the first switching circuit according to a comparison between the output voltage and a comparison voltage and a soft-start circuit configured to raise the comparison voltage from a start voltage to a target voltage during a soft-start phase of the DC-DC converter having a soft-start duration, wherein the soft-start circuit comprises a soft-start capacitor configured to provide the comparison voltage during the start phase, the soft-start capacitor having a soft-start capacitance, an auxiliary capacitor having an auxiliary capacitance, a second switching circuit configured to alternately charge and discharge the auxiliary capacitor with an auxiliary current according to a clock signal having a clock frequency and a charging circuit.

Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

An oscillator circuit includes a current controller, a first capacitor and a second capacitor. A current generator is coupled to the current controller, the first and the second capacitor, and is operable, under control of a control signal of the current controller, provide charging currents. A comparator stage comprises a first input coupled to the first capacitor, a second input coupled to the second capacitor and a reference input to be supplied with the reference voltage. The comparator stage further includes an oscillator output to provide a clock signal based on a comparison of the capacitor voltages and the reference voltage, respectively. A modulation circuit comprises an oscillator input to input the clock signal, a reference output is connected to the current generator, and is operable to alternate between the charging currents, such that a charging current is provided as reference current at the reference output and at least one charging current is provided to alternately charge/discharge the first capacitor and the second capacitor to respective capacitor voltages.